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Showing content with the highest reputation on 07/05/21 in all areas

  1. Hello, I'd like to separate some in-depth research considering sA that started in this thread: https://community.hwbot.org/topic/187148-a7n8x-e-deluxe-as-an-alternative-for-socket-462/ I'd like to discuss some sA and NF2 specific mods to: Make instructions for beginners Investigate other BIOS mods Make some progress if possible I'd like to investigate the work done by gurus like Merlin, tictac and many others, take the best from them and maybe move ahead. It would be very nice to get over 250FSB by tuning system registers and check how it's done. I'll start with some known mods and would like those familiar with ( @Mr.Scott ,@I.nfraR.ed, @digitalbath, @Tzk, @Strunkenbold, @TerraRaptor) to check in and correct if I'm wrong: BPL mod (also NVMM in later versions) - memory init routine from NV. Newer versions are better (up to 3.19?), latest are sometimes incompatible. CPC off (=CR 2T) seems to be modded in BPL. ROMSIP - a set of tables (CPU interface on/off, and for 100/133/166/200 FSB) with CPU and chipset related settings. Influence stability, overclocking, performance. soft-L12 - a mod that acts as BSEL, forcing BIOS to implement FSB200 settings even on FSB133 CPUs. Most mod BIOSes have it, add stability on high bus speeds. modified alpha-timings (can be set using the new NF2 tweaker from Infrared) options ROMs with performance tweaks (3D-fire for example - modified chipset registers?) changed some northbridge registers (S2K control probe limit, XCAARB_RD/WRCOUNT, DQSEN_PULL_B, Auto Refresh Cycle Time, Read-to-Read Command Latency, Pre-charge All Command ) (seen on Asus A7N8X dlx mod BIOS) Please, stay to the topic, don't discuss CPU binning, memory, voltmods and other things. BIOS mods and how they affect the system is the primary goal. Do not discuss cosmetics and general BIOS techniques like opROM update, unlocking menus and so on. I believe we all know how this is done (or it can be discussed in a different topic) so we can focus on advanced stuff. Infrared's Discord channel about Socket A: https://discord.gg/YKHvEt6xct Summary of nf2 registers: https://docs.google.com/spreadsheets/d/1ZDST3XGq0oE7YtQxAME29RtopA8QcePCaHa2NBRHaB8/edit#gid=0
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  2. I bought it mostly for the board, the CPUs are not interesting. The board capabilities are unknown until properly tested. Free up
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  3. This is just a test build. We don't even know, if we need this info in the future. For timings you can use the regular version.
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  4. Reticle site was 1 for all my CPUs. I've made copy and paste from Google docs, width pasted a bit more narrow than in my table, had to make it a bit more wide.
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  5. Again Pro OC was only intended for Extreme "Elite" Overclockers... noone is deleting anyone. With the current config you can still participate in the 2 other stages, so its a mix of both worlds....
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  6. Lots of ways to do this, start here (AB 2.2.4) since you have been trying ABX 2.2.3 This was from UnWinder 680 Lightning On 2.2.4 you may edit Lightning hardware profile files (.\Profiles\VEN_10DE&DEV_1180....cfg) and add the following lines there: [Settings] VDDC_Generic_Detection = 0 VDDC_CHL8318_Detection = 46h VDDC_CHL8318_Type = 1 Those lines disable NVIDIA's capped voltage control module, enable voltage control via direct access to CHL8318 and select offset voltage control mode for it. Note: each card profile must be edited for SLI configs. You can add this to the "OEM" file of many/most versions of AB, I know 411 HWBot works here I think I have one saved LN2 BIOSs FOR THE FIRST 5000 LIGHTNING 680s 80.04.09.00.F7 (non-LN2) 80.04.09.00.F8 (unlocked LN2) AFTER THE FIRST 5000, WE'VE SEEN THESE LN2 BIOSs FROM THE FACTORY: 80.04.28.00.3A (unlocked LN2) 80.04.09.00.3A (unlocked LN2) 80.04.47.00.19 (locked LN2) 80.04.29.00.3A (locked LN2) 80.04.28.00.39 (non-LN2) 80.04.47.00.18 (non-LN2) https://www.overclock.net/threads/official-msi-gtx-680-lightning-owners-club.1280007/ EVC should hook up here ! Have fun 893761724_MSIAfterburner2.2.4.zip MSIAfterburner.oem2 80.04.09.00.F8.rom 80.04.28.00.3A.rom
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  7. CPU model Stepping Week Stepping Locked/unlocked Processor code Major Minor Type EdValue Crystal marker Athlon XP 2500+ AQXEA 0330 WPMW Unlocked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2500+ AQZFA 0411 SPMW Locked Barton 0 2 Locked 2306h AQYFA Athlon XP 2500+ AQXEA 0327 SPGW Unlocked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2500+ AQZFA 0350 SPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2500+ AQZFA 0347 VPMW Locked Barton 0 2 Locked 2306h AQYFA Athlon XP 2600+ AQYFA 0410 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ AQYFA 0410 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ AQXEA 0407 UPMW Locked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2600+ AQZFA 0405 VPBW Locked Barton 0 2 Locked 2306h AQYFA Athlon MP 2800+ AQYHA 0416 UPAW Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon MP 2800+ AQYHA 0416 UPAW Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 3000+ AQYHA 0437 CPJW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ SFF AQYHA 0351 MPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP-M 2500+ AQXFA 0337 XPMW Unlocked Barton 0 2 Locked 2306h AQYFA Athlon XP-M 2500+ AQYFA 0342 MPM Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Sempron 3000+ ADYHA 0512 MPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Sempron 3000+ IQYHA 0444 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA
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  8. These "possible crystal marker" and "possible parent crystal" are just educated guesses based on other parameters. The multiplier type is also probably guessed based on some parameters (major.minor rev, but maybe something else too). That minor revision is kind of strange, I would have guessed higher minor revision would mean a newer cpu, but based on your table - that is not the case. I've added a message box to the tweaker on app open that displays the info I currently have implemented. There's not much info about the topic, but K8 KBDG (BIOS and Kernel Developer's Guide for AMD AthlonTM 64 and AMD OpteronTM Processors) has the MSR register in question documented There's one more value, which is "Reticle Site" and I've included it in the info. Curious to see what different cpus show. Btw, reading and writing MSRs is quite easy. You can use the MSR Editor and MSR Walker in CrystalCPUID tool. PS: I'm thinking of writing a small tool that automatically dumps CPUID registers, MSRs and all the info like cpuid, name, family, model, revision, etc. This way, the comparisons would be easier and faster. Edit: Replaced the app with new build. I was reading wrong part of the register, but it should be ok now. nForce2XT_Debug_20210703.zip
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  9. When i started looking into romsip modding i found this post by TicTac on pcper forums. See attached screenshot for content. So yes, these are indeed multi specific settings... This made me test my FSB stability at multi 7 or 7.5. If it is stable on these multis, then it'll run on any multi. However he didn't state what these settings are actually controlling. If we can find this out (also for the upper half of the romsips), then we might be able to push the fsb further. We also hit a hard FSB wall at about 263MHz right now, on the german Hardwareluxx Forums we got about 4 or 5 boards which won't pass 32M above 263Mhz, no matter what you do. Vdd, Vcore, Multi doesn't matter, some boards do even freeze when trying to set 264/265 MHz. No clue what causes this, might be some peripheral controller or even the chipset itself acting up. broken link: https://pcper.com/forums/?346001-ROMSIP-Table-Mod-Guide#post3100010
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  10. Yes. You basically use the PCI registers of the chipset and set the desired settings via ISA or PCI option rom, right before the OS is loaded. There's two ways of doing this: a) you can just hardcode some settings b) you can write some data from modded bios settings to the CMOS register (bios settings are stored here) and load these cmos values from the option rom. This way you can add additional bios settings without hacking the whole bios. We did this on at least 3 or 4 boards (a7n8x-E, a7n8x v2.0, Abit, Epox?) and it works great. the cleanest solution would be to reverse engineer the bios and add those options in a native way. However i've already spend a bunch of hours looking into this on my A7N8X and even comparing different bios versions hasn't got me anywhere. Luckily Asus made 2 bios versions where each introduced a new bios setting, so the changes inside the code are clearly visible. However it looks like the hex strings which are used to define the bios items and the code which is controlled by them are stored right next to each other. So if there's an option added, then some offsets and pointers will break and the bios won't work anymore. My conclusion was that if we ever want to add completely new options into the bios which don't "recycle" unused bios items, then it's a ton of work. That's the point where i gave up... It's probably better to spend more time upon improving and understanding the romsips first.
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  11. I'd like to add that there's actually two types of nvidia specific code for the ram controller inside the bios, depending on the board and (maybe?) chipset revision. We got NVDAMC and NVMM. NVDAMC is the memory controller firmware up to version 3.19. Nvidia then renamed it to NVMM and introduced version 4.x. Note that these versions are not compatible with each other. So if a board runs on 3.x (examples are Abit NF7, DFI Infinity/LP B, A7N8X), then you can't update to 4.x. Board won't boot. Some newer MSI boards (K7N2?) run on NVMM 4.35 and obviously won't boot on 3.19. I see no reason to use an older version than 3.19. It's the latest available NVDAMC version before NVMM got introduced and runs great in terms of stability and performance. Also note that the NVMM versions (ex: v4.62) extracted from Intel Nforce boards won't work on any socket 462 board. At least that was the conclusion when we tried it in the past. --- If you want to swap the BPL, you can do it with a regular hex editor as it isn't LZH compressed. Thus you don't need modbin to compress it and calculate the checksum.
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  12. Another interesting attack vector is BIOS changelogs. Here is a compare between two DFI BIOSes and their changelog. Looks like the last line about bandwidth refers to changes in offset 5D0h - 1618 has been modified to 1518. Which according to previous data should be SYSDCIN delay (6 -> 5). CPU optimal is said to be more FSB friendly. We can see two things - zero byte (in CPU multi ROMSIP lines) is changed from 69 to 21, byte 5 is changed ED -> E4. Looks like 69 is more aggressive than 21. E4 and ED are known to be of same efficiency maybe it's fine tuning with minor changes. Another interesting thing are changes in chipset part of ROMSIP. Some changes are mapped by @digitalbath : Some are still to be figured out. DFI changelist might be handy: https://forums.overclockersclub.com/topic/115082-dfi-nf2-bioses/
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  13. O.K. looks like I've found the byte 2. This table sure looks familiar if you compare with byte 2 table from above. Still, a long read is ahead. I think I'll take a break. P.S. found a nice list of AMD datasheets, gotta make a local copy of that: https://en.wikichip.org/wiki/amd/List_of_AMD_publications
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  14. @Antinomy thx. Byte 5 effect in speed and memory bandwidth. XB has a lower bandwidth (and latency?) then X4 and XD. DX is in general slower then EX. E4 and ED are equally fast. I am not sure where the difference is. I've combined for my first sips DB to a DD. They're still slow (~EB), but they got a better bandwidth.
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  15. I've made a list from ROMSIPs you've sent - Trats, Shuttle, Taipan, Manta TX, LP_B_619, k12r4, DFI U400s-al, DFI_LP_B (all of them). Here are all the combos for last three bytes: Reds are what I think as typos, anomalies. Though, might help in the research.
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  16. Nice find! No wonder E4 didn't work with 1719. As far as I tested, faster sips E4, ED needs lower values like 1618 or 1518. Slower sips like DB needs higher numbers like 1719 or 1821. You can change the last number from 1518 to 1519 and it will work. It's time to make some tests here. I hope I will find the time to do this.
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  17. O.K. CPU multi part byte 2. Looks like byte 2 is always the same in ROMSIP and depends only on multi: After that, bytes 3 and 4 are 00. But there is one notable exception - DFI (and ECS) that use another writing, in fact, two of them. First is a usual ROMSIP entry, second is an entry modified by DFI, let's call it 3A 02 (by bytes 3-4). The third is another DFI entry, I'll call it CA 02. As you can see, in all cases byte 2 remains the same, only bit 7 is set to 1. In 3A 02 byte 1 bit 5 is set to 1, bytes 3 and 4 are 3A 02. In CA 02 byte 1 bits 5 and 3 are set to 1, bytes 3 and 4 are CA 02. Do not, that only these bits in byte 1 are modified. Other bits depend on byte 0 that are use for optimal/aggressive settings. Purpose of these bytes is unkown AFAIK but feel free to test DFIs modded settings.
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  18. Were you able to set any combinations of values? Seems like they're tied together and you can't set random numbers. Maybe it's my setup. OK, the last three bytes of each multiplier in CPU part of ROMSIP are connected to b0d0f0 rE4-E7. Whice is S2K CONTROL 1 REGISTER. It configures timings of S2K (EV6) bus. But you can't change any bit in the ROMSIP, they are connected somehow. I've had a E4 1618 and tried a E4 1719 setting (1719 from optimal), it didn't POST. Then I changed it to BD 1719 (full three last bytes from optimal) and it worked. Counting from zero, the 6th byte is reg E4 (except the 7th bit). 7th ROMSIP CPU multi byte is reg E5 (with a mask). byte 7 bit 0 is reg E4 bit 7 (RD2WR delay). byte 7 bits 5:3 are reg E5 bits 6:4 Now I need to check ROMSIPs for valid byte combos. So byte 6 controls SYSDCOUT delay and SYSDCIN delay. Byte 7 controls W2R delay and WR data delay. Some ROMSIP bits seem unused by the registers, maybe they control some other regs maybe combined with byte 5.
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  19. I was expecting the last two registers (like 16 18 or 26 18) to be drive strengths for receiver/transmitter aka cpu side and NB side. I have killed two cpus when experimenting with that part of SIP, though should re-validate it by killing another cpu setting it FF FF.
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  20. I'll start myself with the ROMsips. I believe that the table consists of two parts - the first part is chipset-related. The second part is CPU-related. The main problem was that I've been trying to match multipliers to CPU part of the table. Then I've remembered this part. And I've understood that FID isn't endoded in ROMSIP. Instead, FID itself is a link to ROMSIP. Let's look at FID table: So, all multipliers are represented by 16 values that are used by SIP (serial initialization protocol, which is quite advanced). And now take a look at the CPU part of ROMSIP: Do you see this? Multis 11-12,5 (and all higher) have same last two bytes, then 5x and 5.5x are different. The first ROMSIP uses different settings for 6x, 6.5x but the second one has same settings as 5x, 5.5x. So these do look like CPU settings. I believe some of them are delays that are programmed during SIP packet. Might be lame, but I didn't see this info before.
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  21. Galax Hall of Fame 2017 model ( DDR4-4133 ). Binned by Galax. In their box. 4133 / 12-11-11 / 1.98V 4200+ / 12-12-12 / 2.04V 350 Euros shipped to Italy. PayPal fees on you.
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