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Showing content with the highest reputation since 11/05/19 in Posts

  1. 4 points
    Well Brian don't feel bitter about it man, your expertise got seriously abused and false promises were made by you know who. As you mentioned them subscribers, a question pops up: How many gamers have a gazillion followers that would donate money to see this chosen one kick the other n00bs and that can make a living out of it? 100? -200? How many years can they stay on top before having to return to normal life? Out of thousands of Overclockers only a dozen have established themselves as becoming in-house OCers (Sofos, Elmor, Sprave,... ) or kickstarted their other career via OC, (Der8auer, 8-pack), so I definately spot a pattern…. To all of those who think this is the aim of this niche hobby, to make money and get some sort of ROI... I can already tell you: Wrong hobby for sure! We all know who invested shitloads of time and or money to be on top of the league... and even some of them with sponsorship rain into time constraints as family got in the way. On top of that the golden days are long over, The old farts here will remember them good days when when we had several big worldwide compos, requirmement to perform monthly OC demos, etc... Nowadays it's no longer about what you can do, but all that matters now is who you know. Other example how the semi conductor market evolved: the abundant sampling by the big mobo brands or even Intel or AMD samples is only now for the happy few, Not even well respected hardware review sites get their gear anymore via a direct channel. Just enjoy it and have fun. Don't get your hopes high on being the next big thing, it might be very dissapointing in the long run....
  2. 4 points
    Attached is my custom bios for Abit NF7/NF7-S v2.0. I think it should work on v1.x as well, since I've had reports that my older mod bioses work. I will continue with testing ROMSIPs. Changelog, ROMSIP and ISA OROM source code also included in the zip. NF7D_X1-1T.zip
  3. 4 points
    Sorry for the delay: https://hwbot.org/hardware/videocard/radeon_hd_6550d__plus_hd_7670_dual_graphics/ https://hwbot.org/hardware/videocard/radeon_r7_512_shaders__plus_r7_250_dual_graphics/ Also fixed some things: Radeon HD 6380G was incorrectly a hybrid socket, moved to integrated. Beavercreek is now Sumo core. Renamed the added devices from leeghoofd to fit the already used name scheme, e.g. Radeon HD XXX + HD XXX Dual Graphics
  4. 4 points
    This is almost certainly now the single greatest thread we've ever had on this forum I believe
  5. 3 points
  6. 3 points
    Used some of the info and files here + testing and updated the initial post with how to get older images to work on z390
  7. 2 points
    I have sent @viper the latest prerelease version of BenchMate 0.10 and he confirmed that the problem is gone now. As it seems like everybody already has the prerelease version already anyways, you can download it here: https://www.overclockers.at/downloads/projects/BenchMate 0.10-big-v7.exe
  8. 2 points
    You sir, hit the head of the nail. May I add to your writing - Give people food to eat all day, without pain and without the HOW TO knowledge. Preset profiles, preset mem profiles, everything preset. Now, IF the HW AVG Joe is using can by coincidence work with these preset profiles, all good. If not, then the board is crap or the mems are crap or the cpu or everything. Recently, I encountered a case, where an extremely sympathetic guy, expressed the intention to use LN2. Ok. He installed two ram sticks on slot 1 and 3 on a four dimm board and went directly for 4000 / 12-12-12-28-1T ( other timings on AUTO ), HE APPLIED 1.95V and 1.50VccIO and 1.60VccSA ( on ambient water ). NOT HIS FAULT. He was told to do so !!! GOD, felt sorry for the innocent man and did not kill the HW. What is left from us ( old overclockers that started with Celeron 500A ), and went thru huge 20 meters waves and typhoons to finally understand and apply the acquired knowledge to overclocking, have been so highly demotivated by the current status. Start from the basement and climb the ladder a step each time. No, they want the penthouse IMMEDIATELY. I am so sorry
  9. 2 points
  10. 2 points
    If you want to meet up in order to comiserate together on how you once again came third in Country Cup that's fine by me πŸ˜‰ I just wouldn't plan it this far in advance, it's a bit limiting.
  11. 2 points
    Well, I consider myself retired from overclocking... so I don't really care what is considered server and what isn't. πŸ˜„ But as long as you run C2Q or Core i7 in these boards, it should be desktop enough. https://www.asus.com/Motherboards/P5K_WS/ https://www.asus.com/Motherboards/P6T_WS_Professional/overview/
  12. 2 points
  13. 2 points
  14. 2 points
    The comp has started. its too late to change it now.
  15. 1 point
    Indeed, not sure how people expect that being a dick will translate to the hobby growing. Of course there is the more sinister possibility that they want OC to be a members only club with basically no allowance for new members. I hope not because history has shown time and time again that mentality benefits exactly zero hobbies.
  16. 1 point
  17. 1 point
    I'm long over it but with comments like the above antagonist you can see why I've reached F it. The quantity of those type of people have reached all new heights. I am under no impression that streaming overclocking could or would turn a profit. I'm just pointing out that marketing has turned there focus away from ocers in favor of gamers. Those youtube/streamer/ocers trying to sell you mugs shirts and whatever make me laugh because quite simply overclocking is only really exciting to those that see it happen live. As you pointed out the abundant sampling is no more in lieu of this ( i'm still not effected by this however there is a limit to how much time I want to spend on this nowadays thus much less hardware needed ). Action/Reaction the abundant amount of results that use to be done on this sampled hardware ceased to exist. This is an expensive hobby and i'm not even referring to top 20 even top 100 goals will set you back quite a bit so I can guarantee that has played a large role.
  18. 1 point
    @FireKillerGR thanks a lot Stavros 😁
  19. 1 point
  20. 1 point
    Not sure if they all do that, as this is an absolute bitch to get down to fullpot. It has to be walked down in steps to get to fullpot, no crazy tricks/rsvd/etc
  21. 1 point
  22. 1 point
    No pictures from the joint bench session? Who's akujik?
  23. 1 point
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  25. 1 point
  26. 1 point
    You can try and learn it by youself, but Asus designed the REX to die before that happens. πŸ˜‚ Edit: at this point I've given up and moved to EP45T.
  27. 1 point
    @cbjaust I posted about this too in the main CC thread (didn't see your post) - FYI leeg has fixed it now
  28. 1 point
  29. 1 point
    I was thinking something like this*, but I don't think it is optimal if I want to reuse same macros for all settings. It also might be a nonsense and not work, it's jut my understanding. Most of these read/write blocks can be macros, but I don't know how efficient is this code compared to simple switches. Edit: I can probably use dx instead of al in those cmos read operations, so I know dx is always used as a variable for data. EAX will hold my original data, EBX will be zeroed and the needed bits will be positioned correctly, depending on data I want to set, sometimes using BX, BH and BL directly, sometimes bitshifting some of them or using some helper variable (edc for example) for the bitshift and then use OR to set the bits on EBX if those bits are in the higher 16bit segment. Something like that... *Sample code: ; ; Let's assume we want to set tRFC and tRC. ; tRC is 90h, tRFC is 91h, so I will arrange them at the same order they need to be set, just for convenience ; each CMOS register is 8bit ; #76h ; | 000 | 00000 | ; | | tRFC | ; #75h ; | 0000 | 0000 | ; | | tRC | mov ebx, 0 ; reset ebx ; read tRC mov al, 75h ; set CMOS index, basically var x = 75h out 70h, al ; send register offset, 70/71 is CMOS, 72/73 is higher/extended CMOS, for our needs we can use both, since we're dealing with lower CMOS registers and one is an alias to the other. in al, 71h ; fetch cmos data to al mov bl, al and bl, 0Fh ; mask the data and zero the high 4 bits, which we probably use for other setting ; read tRFC mov al, 76h ; set CMOS index, basically var x = 75h out 70h, al ; send register offset in al, 71h ; fetch data to al mov bh, al and bh, 1Fh ; mask lower 5 bits ; we now have bx holding both of our values, something like 00011111 00001111 ; cmp bx, 0h ; check both 0 je codeend ; or some other segment ; else we know at least one of them is not 0 ; get register data mov eax, 80000190h ; move address for 32bit register offset, note no leading zero necessary. It's only needed infront of hex values with letter, so the compiler knows it is not a symbol mov dx, 0CF8h ; pci register address port out dx, eax ; set port we want to read mov dx, 0CFCh ; pci register data port in eax, dx ; read register values ; register data is now in eax and cmos values in bx ; cmp bl, 0h ; check if tRC is 0 je set_trfc ; trfc is not 0 then ; else zero tRC in eax and eax, 0FFFFFFF0h jmp set_trfc set_trfc: cmp bh, 0h ; check if tRFC is 0 je write_data ; tRFC is 0, then tRC is not ; else zero tRFC bits in 91h and eax, 0FFFFE0FFh jmp write_data write_data: ; write data or eax, ebx out dx, eax ; write new custom register value jmp codeend ;
  30. 1 point
  31. 1 point
  32. 1 point
    Price drop 475€ shipped
  33. 1 point
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  35. 1 point
    Great work! The asm code is the easiest part for me, since we have a "template" and once everything is in bios, I can write then write the ISA option rom code. I think that I've got how to add the new labels and options and then update the items in "_ITEM.BIN" in the main bios. Will try it when I get back home. You only need to add in _EN_CODE.BIN the starting addresses of the label heading and first option item, right? SuperBypass seems to be enabled by default on NF7, Data Scavenged Rate is also set to Fast. DS and SR are the same for all DIMMs, but DFI sets them differently for the different DIMMs. Will still need to try more combinations, but something like 4/7 and 6/7 works better than the default 3/10. PS: Your code compiles fine under linux.
  36. 1 point
    FSB is not the problem on this one Does 520+ air...
  37. 1 point
  38. 1 point
  39. 1 point
    Added the known timings in DRAM Controller 1 (B0D0F1). Most are straightforward, except TRAS is controlled with 2 registers. 91:7 controls lowest bit (e.g. 1111 for 15T), while the rest are controlled by 92[2:0]. Also there's not enough space to list all the options for TRFC (32 in total), so I've written just first and last. Will make B0D0F4 (slew rates, drive strengths and the rest) later, but I will probably need to switch to DFI to test them properly by setting them in bios. Also have a PCR file for the Host Bridge by ÁedÑn, but I'm not sure if it is right (10DE01E0). PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32 Copyright (c) 1998 H.Oda! [COMMENT]=Author: I.nfraR.ed, v.1 [MODEL]=nForce2 [VID]=10DE:nVidia [DID]=01EB:Memory Controller (00)=Vendor Identification (01)=Vendor Identification (02)=Device Identification (03)=Device Identification (86:1)=Auto Precharge (90:3)=TRC (90:2)=0000=0T 0001=1T 0010=2T 0011=3T 0100=4T 0101=5T (90:1)=0110=6T 0111=7T 1000=8T 1001=9T 1010=10T (90:0)=1011=11T 1100=12T 1101=13T 1110=14T 1111=15T (91:4..0)=TRFC 00000=0 ... 11111=31 (91:7)=TRAS = TRAS+1 (92:2)=TRAS 000=0T 001=2T 010=4T (92:1)=011=6T 100=8T 101=10T (92:0)=110=12T 111=14T + (91:7) (92:6)=TRCD-R 000=0T 001=1T (92:5)=010=2T 011=3T 100=4T (92:4)=101=5T 110=6T 111=7T (93:6)=TRP 000=0T 001=1T (93:5)=010=2T 011=3T 100=4T (93:4)=101=5T 110=6T 111=7T (93:2)=TRCD-W 000=0T 001=1T (93:1)=010=2T 011=3T 100=4T (93:0)=101=5T 110=6T 111=7T (94:6)=TRTW 000=0T 001=1T (94:5)=010=2T 011=3T 100=4T (94:4)=101=5T 110=6T 111=7T (95:5)=TREXT 00=0T 01=1T (95:4)=10=2T 11=3T (95:2)=TRTP 000=0T 001=1T (95:1)=010=2T 011=3T 100=4T (95:0)=101=5T 110=6T 111=7T (96:6)=TWTP 000=0T 001=1T (96:5)=010=2T 011=3T 100=4T (96:4)=101=5T 110=6T 111=7T (96:2)=TWTR 000=0T 001=1T (96:1)=010=2T 011=3T 100=4T (96:0)=101=5T 110=6T 111=7T (97:6)=TDOE 000=0T 001=1T (97:5)=010=2T 011=3T 100=4T (97:4)=101=5T 110=6T 111=7T (97:2)=TRRD 000=0T 001=1T (97:1)=010=2T 011=3T 100=4T (97:0)=101=5T 110=6T 111=7T 10DE01EB.pcr 10DE01E0.pcr
  40. 1 point
    I took my Z390 Dark Win XP and replaced acpi.sys and syssetup.dll and it gave blue screen 7B with M11A. Seems like reinstallation is required. Edit: My bad, Z390 Dark uses Asmedia SATA while Apex only has Intel SATA. Z390 Dark OS modded with Z390 ASUS files makes XP work on X299 Dark
  41. 1 point
  42. 1 point
    any special volts needed for that or is it all in the lower RAM and CPU multi?
  43. 1 point
    the most fantastic thread ive ever seen written anywhere since being involved with overclocking, id say, im 1 of the 99% that doest understand it all but what a most enlightening thread , hence the few participants in it replying, i cant wait until the next day for the next or the next post to read this is all about REAL over clocking and super smart, clever people that know what theyre doing to achieve the maximum from anything
  44. 1 point
    you probably try to install via USB when USB does NOT work. What firadisk does is that it loads the files into the RAM and treats it like eram/floppy/disk or whatever. That way the installation doesn't have to have access to the USB.
  45. 1 point
  46. 1 point
  47. 1 point
    Is there any difference between the Disco 0.3 Mr.Scott linked and the version you're looking for besides the EB and EBED difference? Or in other words: Would a modded EB bios with EBED romsips work for you? This is the difference between EB and EBED. One table is Cpu Interface on, the other is Cpu Interface off. Every yellow mark is for one cpu multi setting. So depending on your desired multi you may literally see no difference between these two bios versions. The settings are stored like this for the different cpu multis: 11.0 11.5 12.0 12.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 So we can conclude that the following multi settings are different between EB and EBED (from top to bottom): 11x - 11.5x - 12x - 12.5x - 6x - 8x - 10x and 10.5x
  48. 1 point
    Well there are actually quite a bit hybrid graphics cards in the db already and way beyond Llano IGPs only. πŸ˜› But those hybrid thingies get really bad detected by GPU-Z which makes it _maybe_ necessary to increase the requirements of the screenshot. 1. My first proposal would be to remove hybrid from the comp cause its PITA detection wise 2. If we still want to use hybrid, make sure to have a GPU-Z window from all 3 devices - IGP, dGPU, hybrid device 3. If a combination is not already in the db, make a request here.
  49. 1 point
    Why do you think I look like 60 while my Id card says 18
  50. 1 point
    BenchMate 0.9 is here! After six weeks of (absolutely necessary) legwork I'm finally releasing the next major version of my Benchmark Verfication Software. All reported bugs have been fixed, a good part of the benchmark integration rewritten. I also put more effort into supporting Windows 7 and have extensively tested it on multiple platforms. If you like where this is going, spread the word and bench your stuff with BenchMate whenever possible. This is the most secure, reliable and trustworthy option to present your overclocking achievements. πŸ’ͺ Download | Change Log | Donate
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