Jump to content
HWBOT Community Forums

mickulty

Members
  • Posts

    556
  • Joined

  • Last visited

  • Days Won

    3

Everything posted by mickulty

  1. This makes sense but there has to be a consistent standard applied to everyone, not just the new Intel chips. FX chips getting to play in 1 core per CU configurations would show it's not just a way to keep intel competitive for globals.
  2. What rough area are you for collection on the chiller?
  3. If globals are to be divided by core count then they should be divided by core count, that's that. Benchmarks should not be bent to how fast we feel a CPU should be. HWBOT has had big.little for a long time and always handled it this way, the difference is that now it affects a big boy. A mobile CPU is unlikely to be competitive in any global ranking anyway, and if it was that would be a bad thing for the site and community since they can't really be OC'd. Switching to thread count would be pretty reasonable from the perspective of "How do we compare this hardware?", but if that's done I want to know who's going to pick up the task of updating the database. To my understanding it's managed by volunteers at the moment. I don't think the site can reasonably embark on such a thing at the moment. Maybe in the future if the site has had the rewrite, had the bugs fixed that are waiting for the rewrite, and has paid stuff who can do it. Adding a separate hardware listing for disabled cores is not without precedent - after all, that's roughly how unlocking works with AM3. However, we need to think about when hardware qualifies for extra listings. I would propose; "When the average amount of execution resources per core is higher with some cores disabled, and it is possible to disable cores down to this configuration, an additional hardware listing should be added for the highest core count configuration that has the maximum amount of execution resources per core." Why this slightly awkward wording, you might ask? Well, all FX-based CPUs except the FX-4200 have execution resources shared between cores. And yet, unfairly, these CPUs have always had to compete with other chips that have the same core count. An FX-8350 has to compete with an i7-5960X! This proposal would allow an FX-8350 in one core per CU mode to compete fairly with an i7-4770K. It would still get roflstomped, but I think it's important on principle. This way there's a neutral wording, applied to everyone, rather than reference to a specific technology. It feels fairer. The effect is that a CPU with n strong cores gets to compete with other CPUs that also have n strong cores without the weak ones being relevant. The bit about it being possible matters because otherwise you'd get a load of random phone processors involved.
  4. I'm shocked by the CPU restriction, when it said "same platform" I viewed that, as anyone would, to mean socket or maybe chipset. People talk about "all the CPUs on XXXXXX platform" all the time. Please can you announce all the stages ASAP so I know if I have to return my 5600G for a 5700G to be competitive, I was all in on this comp and bought a lot of hardware as well as encouraging others to compete, pretty unhappy to have what's effectively a new restriction dropped only a few days before.
  5. Thank you! For what it's worth all the Cardea SSDs currently on TEAMGROUP's site are; Cardea (in db already) Cardea Zero (in db already) Cardea II (NVMe 3.0 x4) Cardea Liquid (NVMe 3.0 x4) Cardea Zero Z440 (NVMe 4.0 x4) Cardea Zero Z330 (NVMe 3.0 x4) Cardea Zero Z340 (NVMe 3.0 x4) Cardea Ceramic C440 (NVMe 4.0 x4) Cardea IOPS (NVMe 3.0 x4) Cardea A440 (NVMe 4.0 x4) https://www.teamgroupinc.com/en/products/t-force/t-force-ssd#product-box-84 EDIT: As an afterthought: there is the "CARDEA II TUF Gaming Alliance" but that's just a Cardea II in a different colour
  6. I have several SSDs to request the addition of. The SSD database is an extremely long way from complete, but these are disks that actually show up in the 1x AS SSD benchmark ranking at time of writing; Sabrent Rocket 4 Plus (NVMe - different to the Rocket NVMe 4.0) Teamgroup Cardea A440 (NVMe - at least I think that's what @mllrkllr88 is using? It's not the unqualified Cardea...) Samsung PM9A1 (NVMe) WD Blue SN550 (NVMe) HP EX900 (NVMe) Samsung PM981 (NVMe) Sandisk Ultra 3D (SATA SSD) SK Hynix BC501 (NVMe) FWIW I've attached my notes from going through the AS SSD 1x ranking - I'm planning to go through and report the scores that are matched to the wrong hardware once the new disks are added, seems unhelpful to do so before the correct hardware is there to be matched to. However, if strunk or antinomy wants to go through and correct them sooner, the links are in there. micks ssd vendetta.ods
  7. I know I'm sorta double posting here but I want to make a separate post for the on-topic stuff rather than the discussion that needs cleaning. Some community-oriented reasons to stick with 1-core valids; OC is sold to people as "drag racing for computers" - doing everything possible in hardware to get the score, including disabling, makes sense The people who say "yeah but it's only on 1 core" will just say something else like "yeah but it's not stable" instead (a little over 30 tech site comments about giga's score were sifted through on discord and the only one that complained about disabled cores also complained about low cache clock) It means there's a little more refinement/effort/skill to valids Some technical reasons to stick with 1-core valids; AMD and Intel are both pushing high preferred core clocks as a way to maximise gaming performance, so 1-core valids are relevant to the public Future big.little designs may not even be able to run all cores synced, the concept of all cores being at the same clock is on the way out All-core requirements for valids potentially add more ways to bend rules or cheat, like finding a way to keep some cores asleep or move all load off weak cores
  8. They said clearly how it looks, not what it is. You attacked them as if they said that was what it is. EDIT: I wanna add that like, I get it. This has generated a reaction from a lot of people, and that adds up to a very strong reaction. That can be difficult to deal with. Posts start feeling like more of an attack than they are. I think this thread might just need cleaning of a lot of the responses to pro. It doesn't do any good to talk about the conspiracy idea anyway IMO because I don't think it's that relevant anyway.
  9. This is really the only sensible way to approach it IMO, I'd go further and say that you might as well include some stability test as well. @der8auer mentioned on the discord that part of the motive is making the value clear to non-overclockers; The problem is that if you enforce all-core and everything that just becomes; On the other hand, a separate category for measured frequency across a short stability test - not a 'full' test obviously, that would be horrendous for LN2, but maybe 1 minute of prime95 - would probably have much more value for PR. You could also do the same for memory frequency. It's still not 'real' stability because no-one wants to have one error after 5 hours of prime95 on LN2, but I think it's a good compromise where it's relatively meaningful without being horrific to run.
  10. DDR3L isn't relevant here, that's just DDR3 at a different voltage. LPDDR3 is different. I cannot stress enough that DDR3L and LPDDR3 are not interchangeable terms! Fundamentally LPDDR3 is not a Low Power version of DDR3. Rather, it is the third version of LPDDR memory, like how we have GDDR memory. This applies to other generations as well, from LPDDR1 to LPDDR5. The biggest difference I'd point to when it comes to LPDDR3 specifically is that the command/address bus is double data rate, as well as the data bus. Regular DDR isn't getting a double data rate cad bus until DDR5. However there are a number of other details, as this excellent article covers; https://blogs.synopsys.com/committedtomemory/2014/01/10/when-is-lpddr3-not-lpddr3-when-its-ddr3l/. What yos means about data widths is an LPDDR chip can be 32, 64 or even 128 bits wide whereas a normal DDR device is 4, 8 or 16 bits. The cad bus width changes too. Related to this is the fact that LPDDR never appears on SODIMMs, it is always soldered (or stacked in the case of Intel Lakefield's LPDDR4X). As technology moves on we're seeing greater and greater divergence between LPDDR and DDR. We see for example that the Intel i7-10710U supports LPDDR3-2133 and not DDR3, and also supports LPDDR4-2933 but DDR4 only up to 2666, despite a DDR4-2933 standard being available. An older CPU like the i7-8665U supports DDR4 and not LPDDR4, but does support LPDDR3 (and not DDR3). We also now have LPDDR4X standards up to 4266 while DDR4 is stuck at 3200. Because of this I'd come down strongly on the side of saying LPDDRx should be distinguished from DDRx. Maybe LPDDR1 and DDR1 could stay together as their differences come down to more economical self-refresh operation, though I'm not sure LPDDR1 (or 2) are used in anything but phones anyway. LPDDR3, LPDDR4, and LPDDR5 should definitely be separate though, IMO. LPDDR4X is fundamentally the same as LPDDR4 so could be in the same category, although as a database it might be good to distinguish them (this would also prevent stock LPDDR4X frequency subs getting too many points because of being so far ahead of LPDDR4). CPU-Z not being able to tell the difference is a problem, and it's something the CPUID guys ought to look at. It's not the first time there's a problem with CPU-Z, it still calls the Athlon 3000G 12nm Picasso, it's 14nm and a 2-core die.
  11. I'm surprised you got a xeon to OC properly in that thing. Also, try a different GPU/slot maybe?
×
×
  • Create New...