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About Amd_ocer

  • Birthday 01/03/1980

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  1. Best post with the most useful info right there. Thanks!
  2. Well maybe Asus should clarify their voltage expected range with each of their LLC levels, so we dont have to do all this guessing and manual checking work? Ya they should, and that is the root problem, not me trying to get the info I need... Speculation based on lack of info from manuf is Normal. Measuring at socket with a dmm should not be a requirement for 95% of users, unless you are doing hardcore OCing or require some crazy accuracy, which is again, not the case for 95% of users. Otherwise, it is AMD and the motherboard manuf that should tell software engineers how to accurately find and display all these necessary voltages. It is not rocket science, nor should it be the way it is today. You are lucky you are not dealing with hundreds of amps and hundreds of volts otherwise you would be thinking very hard b4 suggesting to use a dmm. Just saying... Ya let me open my case and measure with a dmm every time I need a vcore or SOC reading... far from practical or ideal.. Assuming nothing get shorted....thats what I call silly I been using dmm for over 10 years, for all kind of applications, but this is NOT where I wanna use a dmm while OCing or getting some simple voltages on a $300+ board and a $400+ CPU..
  3. That depends greatly on each MB, I have seen ugly voltage overshooting with LLC being used under load on many boards. Maybe not the Crosshair, I cannot confirm until I get one. I will try to find the measurement points for the DMM once I get CPU / MB... Does Asus even mention what is the voltage variance between each LLC level used? Meaning if it is set at 1.40 in BIOS, what is the range of voltage it would vary between each LLC level used?
  4. I am actually not worried about vdroop: at worst your stress test will fail, at best you save your CPU. I am worried about LLC allowing the CPU to go much higher than the idle set limit in BIOS when CPU is under load. At best it should keep it within that limit, not go OVER it... What MB manuf should do is have 2 vcore voltages: one for idle, and another for load, so CPU will bounce between these two values depending on load. LLC can cause dangerous results especially that we dont know exactly what is the voltage limit for each LLC level, Auto included... It does not help when majority of software are not measuring correctly, so what you see is not what you get
  5. To be more specific as far as LLC, should we try to keep the vcore idle voltage to be THE SAME under load or should it be MORE than the idle vcore (with the help of LLC)..? My understanding is that the higher LLC we choose, the higher voltage overshooting will happen when CPU is under load, which means more potential damage to the CPU, or am I understanding this wrong? I thought the whole point of LLC is to prevent the CPU from going under what is set in the BIOS (cdroop), but it seems LLC is actually allowing the vcore to be MORE than what it is set in BIOS. Can someone clarify all this as far as the CH6 goes?
  6. From what I read around, we WANT the CPU to lower its voltage under stress in order to compensate for the higher current when its under load, otherwise there is higher risk for damaging the CPU with too much voltage. That said, I have to research more to leave the LLC at auto, or to put it to something reasonable for daily usage, like Level 2 or 3. Can anyone comment on their recommendations for LLC for a Ryzen 7 chip to reach something like 3.8 to 3.9 (I dont plan to go further than that)?
  7. Well I gotta read 10,000 posts there to see if there is any software solution that monitors vcore accurately. If you get a chance to measure idle with a DMM please let me know. I wonder if BIOS is still inaccurate. Otherwise, how are we to set vcore for idle and LLC in BIOS if all these numbers are not true to begin with... its all a mess. Ahh good to know, I would much rather leave it at GEN3 with 125 BCLK then. Glad to hear it is working fine.
  8. So let's go with the dmm, 1.399v under load.. that means the set voltage under BIOS for 1.3250 is not accurate if we measure it with the the dmm. Could you please measure the vcore on idle with a dmm?? Just want to know the actual diff between the two when measured with a dmm. Are you sure the tests are not crashing because of vcore dropping more than it should when LLC is at level 3? Just a question, not trying to give you hard time lol For the BCLK, I read that it was advised to lower to GEN2 when OCing the BCLK from 100 to 105-144.. did I misread that?? It makes perfect sense to leave the 1080ti on GEN 3 for that huge bandwidth you have, am just lost how it would still work when we OCed the BCLK to 125. For the 64GB, I was actually praising your setup, not criticizing it, dont take all my comments too personally It is the reason why I will go for 2x16GB for now, in case I would need to add 64gb in the future!
  9. Thanks. Couple questions/suggestions: - What is the actual vcore under load (prime for example)? - Any reason you chose Load Line Cal. at Level 3 and not 4 or 5? It might give you more stability under stress tests, maybe worth a try. - Any reason the PCIex16 and x8 are left to GEN 3, I would assume at 125 BCLK you would want them set for GEN2? - You are running 64GB otherwise you could have got much better frequency and timing with the type of RAM you have. Still 64GB with 14 timing and 3000 is excellent!
  10. This is the setup I was aiming for. Can you post your exact BIOS settings in terms of the memory, PCIe, and so on please?
  11. From what I read around, under 115-120 is just fine for daily, and it will keep your PCI under GEN2 which is fine even for cards like the gtx 1080ti
  12. Got it. So it is mainly because the current 3200 divider is not working as expected, otherwise we would not theoretically need to go 2666 in order to have better mem frequency or latency. So maybe in the future that would be fixed by BIOS updates and we would not have to go to a lower mem divider, OR raise the BCLK. Now it all makes sense. Lastly, are the memory latency issues with having 2 CCXs been addressed yet? I use a lot of VMs and I would like to know how Ryzen fairs in terms of fast memory transfer between its own CCXs and the main memory...
  13. Here is another example: why would someone with the following kit F4-3200C14D-32GTZSW use a BCLK of 131.4 and a divider of 2133, just to reach a DDR4 frequency of 2803, when his kit supports the 3200 divider in the first place.. Lastly, I read that when increasing the BCLK on the CH6 board it would automatically downgrade the PCIe to GEN 2, is that true, or it would have to be manually changed?
  14. What I dont understand is the calculation of the mem divider vs the memory frequency on Ryzen. For example, if I have a kit that is 3200CL14 or CL15 and my target DRAM is also 3200CL14, and the board supports a divider of 3200, why would I mess with the BCLK at that point? In which case one would lower the divider to 2666 from 3200 on a 3200CL14 or 3200CL15 kit, and for what purposes?
  15. ^^ In your example, what is the "stock" DDR specs and speeds? Would not raising BCLK to 140 causes everything else to be affected, like PCI devices, and so on... Seems like counter-productive at that point.
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