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P67/Z68 BIOS collection


Massman

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Using the latest .174 BIOS from MSI on the P67A-GD65, using ratio x50 or over it gave me PXE-E01 error. No matter what voltage adjustment altered didn't help. sigh.

 

Edit: Enabling the PPL option works. Value keep Auto.

Edited by Sanko
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Anyone using Gigabyte GA-P67A-UD3P mobo ?

I'm thinking about buying one. But not sure It'll able to OC or not.

There're only UD4 UD5 UD7 update on first post that fix PLL. And this F5 bios you say it's not fix that. =/

 

If anyone have any further progress please let me know too. thank you.

Edited by kurayami
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Hi guys,I will upload soon on TT forum new beta BIOS for P67A dated 11.January.

 

GA-P67A-UD7 - F7a

GA-P67A-UD5 - F6a

GA-P67A-UD4 - F7b

GA-P67A-UD3 - F6a

GA-P67A-UD3P - F6a

GA-P67A-UD3R - F7a

 

-Support "Internal CPU PLL Overvoltage"

-11.Jan 11

 

Edit:

-it's also on Gigabyte site

Edited by stasio
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welcome to 1993; first Pentium released, locked multiplier, locked FSB, than came the motherboards with unlocked FSB option

Intel has completed their plan to commercialize overclocking, it was a long road, but now they finally did it;

AMD has already done it when the launched their Black editions. Now Intel has perfect control over FSB, Multiplier and no motherboard can overcome the limitations set.

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Massman, what do you name under "Sandy bridge technology"? Can you name the parts that you mean under this?

 

Now Intel has perfect control over FSB, Multiplier and no motherboard can overcome the limitations set.
Show be read as: Now Intel has perfect control over FSB, Multiplier and no motherboard can overcome the limitations yet.
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Antinomy - Everything integrated on the CPU as well as integrating a single clockgen into the P67 chipset.

 

The problem is that everything within the CPU package is running at the same BCLK, much like in the past we had no control over PCI/AGP clock frequency so everything runs 1:1. The clockgen Intel integrated in the P67 is a normal CK505, very similar to what we had on P35/P45/P55/X58. That type of clock generator actually has 'straps' build-in, meaning Intel should be able to open up dividers for this platform where necessary. Perhaps we should hope for a mainboard manufacturer to reverse engineer the P67 chipset :-).

 

As far as I understand from reports on the LGA2011 platform, they will be integrating the dividers in the next platforms so BCLK is fully open again.

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What I've been thinking about today is - why can't the CPU be pushed if everything else can?

 

http://www.xfastest.com/cms/tid-55340-5/ - I can see a 200MHz overclocked system on a P67, do you? ;)

 

That's what I was talking about - if this can be done on 1156, why not do on 1155? I thought that the clock were bound inside the chipset, not CPU package. If what you say is true then it's another case and yes, nothing can be done. But... :D

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How it the clockgen implementation on that Asrock board?

 

The clockgen integrated on the P67 is not the key problem. Even on the most recent P55 boards, the clock generators have strap setting to run at 400BCLK (~ P45/X48). The problem is that this the clock generator is locked to 1:1 thus running all components at the same base frequency. Therefore, increasing the BCLK equals increasing the frequency of all the components on the CPU package (eg: USB, PCIe, DMI, ...).

 

The LGA1156 Lynnfield and Clarkdale architecture is a lot simpler in terms of clocking. I'm pretty sure that Asrock implented the P67 as simple P55+Clockgen+extra features. As said before, the type of clockgen Intel integrated in their P67 chipset is the same design as we've been using on P45, P55, X48 etc. It's not strange that Asrock manages 200+ BCLK.

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How it the clockgen implementation on that Asrock board?
I assume they've traced clocks to external PLL instead of integrated. This means that the clockgen pads and contollers (DMI/PCI-E/SRC (SATA)) clock inputs are not connected on die but are output on package pads. It's the easiest explanation. Another one is that QPI controller is in the CPU while all others are in chipset. Then external PLL is used for clocking the CPU while P67 clockgen is used for it's stuff. But the classical placements of the clock generator on the PCB makes me think that the first idea is closer.

 

Time to write a letter to Asrock support begging them to make a right board with external PLL for SB? :D

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