July 22, 20205 yr So I'm very new to memory OC, and I've been trying to get some PSC to work for me. I've made 100+ 32m runs with this pair of sticks over a couple of weeks on air, testing the effect of each timing I tweak and OS tweaks. I have tried up to 2.05v once to see how high vDIMM they will take, but all the rest has been 1.92 or a little lower, min for stability. Vcore 1.31 / 50x Vcache 1.42 / 50x Vin 1.72 VSA .05 VIOA +.16 VIOD -.08 I have 10 sticks of PSC, the lowest volts for the binning profile was 1.83 for 2 of a triple kit of 2000c9 ripjaws, those are what I'm using. (My one living stick of patriot 2400c9 took 1.89v) I started from my "binning" profile "2666 9-13-9 ultra loose", and have been tightening from there, I got to 8-12-8-28-1-88-11750 tWCL 6, tRRD 4, and then the stability problems started... Been pulling my hair out trying to find out why they won't do what should be simple secondary timings like tWR <16, tRTP <6 etc, and now I'm getting out of round with just the basic 2666 9-13-9 ultra loose profile with a fresh OS. Have a killed them?
July 22, 20205 yr I would suggest dropping cache and core to 4GHz when testing ram. I'm not sure that 5GHz cache on ambient is particulary stable tbh. Also, typically PSC responds to IOA and SA being low and IOD being higher. VCCIN also seems quite low, I normally run 1.8-1.85V when testing ram - as it influences stability. In addition, make sure to manually set the RTLs/IOLs as otherwise they might vary and throw your results all over the place on efficiency/stability. Edited July 22, 20205 yr by Noxinite
July 22, 20205 yr Author 3 hours ago, Leeghoofd said: Incorrect training? Cleaned the gold contacts and dimm slots? 22 minutes ago, Noxinite said: I would suggest dropping cache and core to 4GHz when testing ram. I'm not sure that 5GHz cache on ambient is particulary stable tbh. Also, typically PSC responds to IOA and SA being low and IOD being higher. VCCIN also seems quite low, I normally run 1.8-1.85V when testing ram - as it influences stability. In addition, make sure to manually set the RTLs/IOLs as otherwise they might vary and through your results all over the place on efficiency/stability. 5ghz cache seems stable, but gives no discernible benefit over 4.8ghz. But it might be a good idea to just go to 4ghz to take it out of the question. I'll try other voltage settings later, maybe this evening. The reason I was doing min stable IOD is that I found that less IOD = higher max vDIMM, although that was with BBBG. I've left no timings to training, RTL/IOL are at 40-41-4-4, and terts are 6-6-6-18-5-5-5-6-6-15-15-15-13-2-2 IIRC. Fast boot is still off however. These terts are from my ultra loose binning profile and they're 100% stable, since they've been set that way while running pi ~100 times so far. When you are testing memory, how many runs do you do to test the effects of a tweak? I've been doing 5 runs with full optimizations+waza. More runs = smaller margin of uncertainty, but it's very time consuming. 4ghz will make it more so
July 22, 20205 yr 4 minutes ago, nnimrod said: 5ghz cache seems stable, but gives no discernible benefit over 4.8ghz. But it might be a good idea to just go to 4ghz to take it out of the question. I'll try other voltage settings later, maybe this evening. The reason I was doing min stable IOD is that I found that less IOD = higher max vDIMM, although that was with BBBG. I've left no timings to training, RTL/IOL are at 40-41-4-4, and terts are 6-6-6-18-5-5-5-6-6-15-15-15-13-2-2 IIRC. Fast boot is still off however. These terts are from my ultra loose binning profile and they're 100% stable, since they've been set that way while running pi ~100 times so far. When you are testing memory, how many runs do you do to test the effects of a tweak? I've been doing 5 runs with full optimizations+waza. More runs = smaller margin of uncertainty, but it's very time consuming. 4ghz will make it more so Tbh I just set a tight profile and bin for minimum dram volts without wazza, and I only do 1 or 2 runs at each voltage depending on how consistent the results are - PSC and samsung seem fine with this, but BBSE can be a pain as it is so inconsistent in the first place with OC and voltage tolerance. Edited July 22, 20205 yr by Noxinite
July 22, 20205 yr 32m alone is not really telling on stability. The tighter you go, more surprises you get - and sometimes you need to go back and revalidate stability of previously adjusted timing you thought is stable as the timing you are adjusting now is affecting in as co-dependence. I was using multithreaded tests (hyperpi, hci memtest) as it gives better idea of stability.
August 4, 20205 yr You don’t need to run a full 32m result to test efficiency of a timing or sub timing, I normally just run 4-5 loops to test efficiency.......I’ve done this on many platforms with no waza, my latest testing was on AM3 that wasn’t to long ago...was no way I was waiting for 16min runs to finish each time ahah This goes for all other efficiency testing I do 3D as well, test each test....along with all OS tweaks
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