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Figuring out AMD's equivalent to RTL and IOL (RDL and MRL)

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I'm looking into AMD's equivalent of RTL and IOL, which are RDL and MRL. I remember @chew* and @I.nfraR.ed mentioning these were configurable in OS on K10.

I have now found evidence of two sets of memory, when training the exact same configurable timings and voltages, reporting different RDL and MRL. 

I have video of this property in the in the 7-zip file included in the post.

I have also uploaded both videos to YouTube.

Here's a better picture of what the Ripjaws were running when passing benchmarks:


Running mixed sticks would report different RDL/MRL in bios, depending on what stick is where, but Zentimings reported the same. Running only Neos would not enter OS.

I noticed that the set of Neos trained far more consistently, and I'm curious if RDL and MRL have anything to do with that.

My friend at MSI pointed out a couple settings to me:

DRAM Latency Enhance, I believe this is similar to having RTL enabled in bios to be configured when set to manual.l

ARdPtrInitVal, what he referred to as DFI.RX.MP_

I believe MP1 is equivalent to IOL offset on Intel. It had a range from 0 to 127, but I could not measure what the default value is.

MP0 also appeared to be equivalent to something on Intel. It had a range from 0 to 15. I remember there being another setting next to IOL offset on Intel with the same range, but on Intel changing it would not boot at all. I also cannot measure the default value of this.

RxDatChnDly may be relevant as well. The only settings shown were 0 and 1. At jedec, bios would report 0, and at manual OC, it would set 1.

Unfortunately, none of these settings in bios would change the reading of RDL and MRL. I think the settings are either non-functional, improperly implemented, or blocked by AMD.

I would like to hear if anyone has more information or experience on this, finding a way to control these settings could be pretty huge.


Edited by Sparky's__Adventure
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