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about P45 chipset memory div 3:5 bug


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We all know that P45 has memory div 3:5 bug, but I still wonder:

1. Does this bug exist in all P45 boards? For exmaple, is in all DDR2 and DDR3 board? is in all chipset rev. A2 and A3?

2. If not all P45 board have this bug, how can we confirm that when we use 3:5 ?

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I did some memory bandwith test by AIDA64, I don't think it has 3:5 bug for my EP45T-UD3R

 

1. E8400 (500x6), 400 strap, div 3:4, DDR3 1333 6-6-6, PL9

EP45T-500FSB-3to4-1333.thumb.png.d92b91c3c200e050735f107d5ccb835f.png

 

 

2. E8400 (500x6), 400 strap, div 3:5, DDR3 1666 6-6-6, PL9

EP45T-500FSB-3to5-1666.thumb.png.b38e249faee842d77a2c14a64a5ec983.png

 

 

3. E8400 (500x6), 333 strap, div 5:8, DDR3 1600 6-6-6, PL9

EP45T-500FSB-5to8-1600.thumb.png.a68486ddbabce44c71efb8a04f9ff7f6.png

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What would happen when you compare strap 400 2:3 vs 5:8 vs 3:5?

If it's not bugged then 2:3 < 5:8 < 3:5 in terms of speed, but if it's bugged then 2:3 ~ 3:5 < 5:8, isn't it?

 

Edited by frag_
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54 minutes ago, frag_ said:

What would happen when you compare strap 400 2:3 vs 5:8 vs 3:5?

If it's not bugged then 2:3 < 5:8 < 3:5 in terms of speed, but if it's bugged then 2:3 ~ 3:5 < 5:8, isn't it?

 

Well,if FSB and Mem freq is almost the same, then I think mem performance should be strap 400 < 333 <266 < 200. But if FSB and Mem freq scares too much, things will become complicate.

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8 hours ago, TaPaKaH said:

@wytiwx So, setting #2 is actually 750MHz / DDR3-1500 mem speed, which falls perfectly in line with the DDR3-1333 and DDR3-1600 results you've posted :)

Is mem bandwidth of 750MHz/DDR3-1500 the experimental results?

But in other words, if we have to use 3:5 for efficiency rather than raw mem freq in particular conditions, it doesn't matter whether there is a bug or not.

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