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Intel Haswell Overclocking Fully Disclosed - Theory For Core i7 4770K!


Massman

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If BCLK OC means that the times of fun overclockable cheap chips (Haswell based Celeron's/Pentium's) like the ones of "775 era" is back, the only thing I have to say about this platform is:

 

shut-up-and-take-my-money.jpg

 

:D

 

there are probably steps like x79 100, 125, etc for the bclk and they might not be as flexible straying away from those steps. I assume they would lock that down on cheap chips..just conjecture though :)

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there are probably steps like x79 100, 125, etc for the bclk and they might not be as flexible straying away from those steps. I assume they would lock that down on cheap chips..just conjecture though :)

 

Sure, but it's always better than actual 100+/-10% BCLK OC that we have with 1155 Sandy/Ivy and that would make the cheap chips oc able. But being somewhat realistic, I don't expect to see Intel allowing BCLK OC on these cheap chips too...:(

 

But well... The hope is the last thing to die! :D

Edited by NoMS
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Overclocking has become just another product feature that Intel can charge for. Just like

 

- hyperthreading

- amount of cores

- amount of cache

- type of IGP

- virtualisation

- dram ratios

 

And so on.

 

There has been no confirmed (or leaked) product information regarding the correct configuration of the SKUs, just guesses, so we can only make assumptions here. But it seems fairly obvious that the non K-sku processors will not have the option to play with PEG:DMI (bclk gear ratio) settings.

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The 3820 has gear ratios despite being a non-K, so some of 'em might. Almost certainly not the low end stuff though.

 

Hah, same response I had :D.

 

I was made aware of the fact that the Core i7 3820 was part of the most high-end desktop platform and that Haswell is a replacement for the mainstream platform. Between the lines, it probably meant that all non-K sku CPUs built for a high-end X-chipset will have additional overclocking options compared those for a mainstream Z-chipset.

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IDF 2012 docs say that L3 cache is on ring frequency and power domain. IDF2013 China docs say L3 is on core domain. I think the former is correct?

 

BTW, what you call eDRAM is not on-die (it's a separate die on the same package), also the small e for embedded is not exactly correct, since it's a separate die :)

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IDF 2012 docs say that L3 cache is on ring frequency and power domain. IDF2013 China docs say L3 is on core domain. I think the former is correct?

 

BTW, what you call eDRAM is not on-die (it's a separate die on the same package), also the small e for embedded is not exactly correct, since it's a separate die :)

 

Thanks for the corrections. L3 must be on Ring frequency as it's shared between all cores.

 

There wasn't that much information on the eDRAM - even behind-the-scenes. All the info we got was "additional cache", "in-house design" and "super dooper fast".

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