BOBKOC

& CPUID =↓? +rename mcupdate_GenuineIntel.dll to mcupdate_GenuineIntel_1.dll + restart Win & check MCU

no avx512 if no MCU 15 in HWinfo? it is possible for the G6900 to have its own MCU(&CPUID) for avx512

And you never will. +check p.m

any bios + microcode https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=611292

try csm disabled+secure boot disabled then csm enabled + save&exit

CPU_VDD2=1.35v & CPU_VDDQ=1,45v or CPU_VDD2=1.45v & CPU_VDDQ=1,35v ?

+ "Reading from the GDDR5 memory module occurs in blocks. The minimum block is now 64 bytes, which is due to the size of the cache line of the processor. This block can be read both from one bank and from different ones. 1. tRAS=tRCD+tRP (when reading 16 bytes from one bank) 2.! tRAS=tRCD+tRP+8 (when reading 32 bytes from one bank) 3.! tRAS=tRCD+tRP+24 (when reading 64 bytes from one bank) 4. tRAS=tRCD+tRP+56 (when reading 128 bytes from one bank) For DDR5, the optimal choice is the 2nd or 3rd option." my optimum ->3.

&t_cores<=90С ? & after PowerDown(without electricity supply +-1min) ? &tRAS = tRCD + tCWL + tWR ? + https://www.overclock.net/threads/official-intel-ddr5-oc-and-24-7-daily-memory-stability-thread.1794772/post-29183838 & DRAM_VDD(+) =1.525v & DRAM_VDDQ(-)=1.35 V ?

+ test(1'st on stab frequency) DRAM_VDD - DRAM_VDDQ =0.2(best case scenario=good memory chips) to 0.1(normal) to ... if the reduction is excessive(or not?) or low DRAM_VDD, the RTL increases(+1)

If on F23a same thing("6E d5 train fail in all bios") ... then the fun really starts?

or 13600? .... & with odt&others from https://yujihw.com/review/gigabyte-z790-aorus-tachyon-ddr5-oc-8400c34 ?

no?"1/ flash by Q-Flash Plus => https://disk.yandex.ru/d/bkj31DC0kmPxCA " for the future:

1 ->!!! https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=634699 & for the future

https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=634633 for mem+, try F23a official first(or https://disk.yandex.ru/d/bkj31DC0kmPxCA by Q-Flash Plus) & setting tricks from https://yujihw.com/review/gigabyte-z790-aorus-tachyon-ddr5-oc-8400c34

Me? for you & F23a - need(save your profile(s) on usb for later back) &↓↓↓↓↓

https://yujihw.com/review/gigabyte-z790-aorus-tachyon-ddr5-oc-8400c34 to the pile? for ODT & ...

1/ for mе - good, OC buttons - work( +- 100Mhz CpuFrequency or +- 0.1 BCLK if selected in the bios), but I don't use it. 2/ I don't know, my optimal ratio on any last bios is 6400@7200(VDD=1.51v/VDDQ=1.49v+VDDQcpu=1.38v/VDD2cpu=1.38v&SA(avto)=1.25v) for 2х16GbHynixM-die+12700kf 3,4/ 690->790&790->690 only by FPT like https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=634699 & after 790(on690)->790(new ver bios) or 690->690 as normal

https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=634055

if desired, you can use z790bios

https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=629856 https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/page/11/#comment-629089

F22 - possible, thanks to X6h &winraid

Right after F22+avx512

after X3K, analogies are not appropriate here

simply, no one tests Xbios+12700** , otherwise +1 => https://community.hwbot.org/topic/210084-gigabyte-z690-tachyon/?do=findComment&comment=629252

I have found for me&12700KF, the problem of all Xbios after X3K - E-core on. therefore, I have disabled the e-cores in the bios for firmware and have no problems with the 1start after Q-flash plus & other options, Load Optimized Defaults or CMOS_SW. in addition, F21=no memory errors, X6h =memory errors?, all things being equal.