Unexpected tRAS and tRC

[Zenefess]

Now that we're well into Autumn over here in NSW Australia I decided it was time to tighten the living s##t out of my memory modules (CMK16GX4M4B3000C15). After 2 days of tweaking/testing I reached the following timings:

And here are the benchmark results:

 

After updating the mobo's BIOS to the latest revision, the PC couldn't complete POST.

I Added 10mV to RAM; POST now completes, but there are errors during test 7 of memtest.

Changed tRFC from 300 to 304; errors don't occur until test 13.

Changed tRC from 8 to 9; no errors after 4 passes.

Subtracted 10mV from RAM; no errors after 4 passes.

Played with a few timings and managed to reduce tWTR from 4 to 3. I also set tCKE to 8 (about 5ns).

 

Here's the (best of 3) benchmark results:

C-state 1E was enabled; maximum "North Bridge Clock" is actually 3602.1 MHz.

 

The benchmark in the original post was best of 3, so I may have actually gained a negligible boost to throughput; likely due to the reduction in Write-to-Read time.

 

Anyone else able to reduce their tRAS and tRC this much?