GTL Voltages, Questions Regarding Them

[ultra_code]

Hello,

First of all, this is my first post on the HWBOT Community Forums. I've been submitting OCing results to HWBOT as a hobby for the past year or so, slowly learning the ropes of different platforms (mainly pre-UEFI-era, e.g. Socket A, 478, and especially 775). Sorry if this forum category is not the best for this post, and please go easy on me if some of these questions should be obvious.

Now then, the meat of the matter. As of late, I'm try to get more out of my S775 OCs on water with my Asus P5E3 Premium, and one of things I haven't touched until now are GTL voltages (VTT and the ratios dividing it). Guides on the matter from Edge Of Stability and this Xtreme Systems forum post have helped me wrapped my head around the concept of GTL voltages and such somewhat, but there are still lingering questions I have regarding them. I'm hoping someone here with more experience than me could answers some of my questions.

1. Rather basic question, but where exactly is the GTL circuit(s) located? On the CPU, the northbridge, southbridge, or somewhere else on a motherboard by itself? Are there separate circuits for both the CPU and northbridge, or is it just one circuit handling both? Do they like being cooled, or do they like being ran warm like NAND flash on SSDs?
    
2. Just for clarity, what are the functions of the "data strobe pins (GTLREF0/2)" and "address strobe pins (GTLREF1/3)"? Also, in the above-linked Xtreme System's forum post, it states that the address strobe pins should be given at a lower voltage/ratio than data pins - could someone vouch for this statement? Any tangible recommendations by how much address strobe pins should be kept below the data strobe pins?
    

   Quote

   Address strobe Pins (GTLREF1/3) will generally tolerate small variance with respect to reference voltage accuracy, and should in most cases be setup a little lower with respect to Data strobe Reference multiplier or voltage.
   Why?
   Probably the same reason as any other reference or input voltage for clock strobes, signal resonance or cross talking.

   
    
3. Is it better to have lower VTT and higher ratios to compensate, or higher VTT and lower ratios? I'd think the former, but just want some confirmation.

 

If anyone could answer any of these questions, I'd appreciate it. Thanks!

Edited January 21, 2022 by ultra_code

[CL3P20]

Gunning Transceiver Logic:  is a driving strength for core IO.. its important function is to reduce jitter/noise in the circuit which will occur at different voltages and clock speeds. Its a function of the mobo into the CPU.

 

 When youre adjusting GTL.. you need to understand how to calculate the actual GTLv you are creating. Every time you adjust VTT.. you have to recalculate GTL, as the produced GTLv is a ratio of the set VTT. Some CPU you will only need to tweak GTLv for 1c to make CPU stable.. others more. If youre running wprime and see 1x core far behind or ahead of others.. pay attention to it. GTLv settings will bring all cores into sync or push them out.

 

 In regards to your VTT question - it varies from mobo type.. as some have worse VTT circuit/droop than others. For cold benching wolfdales.. I typically run 1.38v - 1.47v for VTT and set the GTL for what i need after that.

[ultra_code]

2 hours ago, CL3P20 said:

Some CPU you will only need to tweak GTLv for 1c to make CPU stable.. others more. If youre running wprime and see 1x core far behind or ahead of others.. pay attention to it. GTLv settings will bring all cores into sync or push them out.

I've ran into that situation a few times in Cinebench 11.5 (my current default benchmark to run at the moment on S775). Good to know that's what's causing that behavior.

Since the original post, I've refined my understand/technique of dealing with VTT (through OCing more quads, of course). I know that CPUs like a certain... range, and it's best to try to maintain it as best as possible. Seems like 45nm quads love VTT (scales with clockspeed, and can save some Vcore in exchange for VTT), whereas the two 65nm quads I've tested are not the least bit interested in any more VTT above the stock 1.2V at around 4Ghz (maybe I'm not at the point where VTT matters for them, maybe they actually need loads of VTT and I've been mistaken, not sure).

I suppose my third question in hindsight is a bit silly - why wouldn't you want the lowest VTT you can get away with? Still, if anyone has an edge case where higher VTT for lower ratios is beneficial, let me know.

As for the first two questions, I guess I'm asking about something few people know about... :/

Edited February 2, 2022 by ultra_code

[CL3P20]

The difference in GTL on the same CPU but different mobo is what led me to think that its not so much about the CPU..obviously if its not happy it will crash, but the reason for tuning GTLv at all... is the mobo! While id agree that 'yes' you do want the lowest stable VTT..but that requirement is for the CPU directly, whereas GTLv is only used to "fix" the noise created through the VTT circuit and bring the driving signal back into spec. Lets face it.. 775skt wasnt 'the pinnacle' of engineering/design lol. If the board has 'dirty' power phases that introduce a lot of jitter into the electrical signaling, you get poor results. Its no coincidence that the best boards for OC [even then] have premium power components. 2x of my favorites for DDR2/775 are the Gigabyte DQ6-X48 and the Asus Maximus II Formula.

 

**to answer your Q.

#1. GTLv is 'made' at/in the CPU by augmenting the VTT. On premium boards, the VTTv will be a single power phase near the NB.. which also has its own power phase [2x mosfet]. Yes they like to be cool..no more than ~40c though as NB will typically cold bug. LN2 or DICE on the NB helps tremendously with memory OC. I would run 1.48v NB for 1300mhz CL5 with cold.. 1.38-1.42v NB for 1200mhz CL6 on air.

#2:  GTL#0/2 and GTL#1/3 are in reference to the channels used by each CPU core respectively

Edited February 2, 2022 by CL3P20