Falkentyne

Doesn't the M12A have two separate ME chips (corresponding to the main and backup bioses the chips are linked to) that can be force flashed by the EVC2 device with the ME firmware? They are separate from the BIOS chips. Just do a "read" on the chips and check the file size then you will know.

Hmm 0705 beta bios for Apex. That must be the test BIOS shamino released to fix some things. Is there one for the Extreme also?

With my 10900k, RTL's changed on M12E 2004 (and I assume M12A 2004 too), so what I previously used on all older bioses, 1002, 1003, 070x 060x and so on, 62/62/63/63 //7/7/7/7, for 2x16 GB @ 4400 16/17/37 1.5v, on 2004, when I tried this, the system was wildly unstable, either crashing in BIOS or BSOD/UEFI missing winload error. Had to use 63/64/8/8 now on M12E 2004. I am assuming (but do not know for sure) that this applies to newer ones too. On M13E, I used the exact same RAM settings and 63/64/8/8 with 10900k, as I did on M12E 2004, and it was just as stable (just needed 20mv lower bios voltage due to less vdroop/new VRM/intersil at same LLC). No problems. Same ODT's too (80/48/40). With 11900k RKL and M13E, everything's different. At 4266 16/17/37, some of the tighter terts that worked on 10900k just fine cause a massive drop in speeds, (I think trdrd=5 is bad on this) so those have to be loosened. the ODT's also caused instability, 80/48/40 was no longer stable, but Auto was fine. Either manual RTL's don't work, at least no one has figured out how to make them work. RTL Init no longer works at all. "Round Trip Latency Timing" Training algorithm does work though.

Are you guys talking about this? https://1drv.ms/u/s!AkQqWXPLNfg-ghKwD718Q1gHFWEc?e=cRZnz5

They are the same setting. I've seen several "sub" parameters for that setting with absolutely no documentation on it on some laptops, I think I saw three looking at a MSI laptop BIOS with AMIBCP 5.02. I only remember a 0, 1 and 2 however. Or perhaps the 'first' one had recommended values of a 0,1,2 on some strange Asus BIOS and the second was like 5,6,7 I honestly don't know or remember. hard to remember bios settings with absolutely no documentation. Ok I found it. DLLBwen[0] for 1067 (0...7) -->failsafe: 0, Optimal: 0 DLLBwen[1] for 1333 (0...7) -->failsafe:0, Optimal: 1 DLLBwen[2] for 1600 (0...7) -->failsafe:0, Optimal: 2 DLLBwen[3] for1867 and up (0..7) -->failsafe:0, Optimal: 2 Don't ask me what any of that means.

Well the other two vcore readings are useless. VR VOUT (and Current IOUT and Power POUT) are the readings you want. You also obviously need Dram, VCCSA, IO and those others. I have no idea about your speedstep problem. I disable speedstep on every gigabyte bios and I never had an issue like this. I tested X4 briefly and some others. Maybe you need to enable Turbo boost ratios manually and keep those at auto.

With that board, please use HWinfo64 and use the VR VOUT field in the VRM section for accurate voltage monitoring. This is the "die-sense" voltage that you may have heard of, and it is extremely accurate. it is the VRM ADC controller value. **YOU MUST** be using the most current version of hwinfo64. Older versions will not support VR VOUT. VR VOUT only got added because I asked Martin to add support for it, but he had some difficulty accessing the VRM. Shamino (Asus), believe it or not, helped him get it working on a *gigabyte* board. yeah, Ironic, I know. The vcore you see in CPU-Z is the old typical "Super I/O" voltage reading which is always going to be above or way above what the real vcore is. In fact, in HWInfo64, there are going to be three vcores: 1) Super I/O reading (ITE 8688E). 2) Socket MLCC reading (ITE 8792E). 3) Die-sense reading (direct from VRM) - Intersil 96269 (I think). The die-sense reading is the reading you want to use. Unfortunately, no other programs know about accessing the VRM directly, just hwinfo64. ------ I also do not use speedshift or speedstep. I disable all of that stuff like you told us to do on NBR long ago. I just disable all power saving and set a multiplier randomly. Also, one thing I noticed on Gigabyte boards is that the "Turbo velocity boost" multiplier boost seems to be enabled by default regardless of cpu temps. For example, at "stock" operation, the gigabyte boards will turbo to 4.9 ghz at all times, instead of it being 4.9 ghz < 70C and 4.8 ghz at 70C+. I'm not sure if this affects the "2 core" 5.3 ghz boost however.

The Great Mr Fox. Please use "Fixed" mode, not "override" mode. Override mode changes the VID to the override value. This is identical to "override mode" on your Clevo laptop, oddly enough. If AC/DC Loadline are not set to "1" (0.01 mOhm) or a low mOhm value, that will cause vcore to rise substantially at load, even more so if LLC calibration is higher than "Standard". Fixed mode is the "override" you were used to on Z390 desktops. That's actually what you want to use.

You need to -uninstall- 4.0.4, not just install 4.0.3. Uninstall both. Reboot after each. Then install 4.0.3. Reboot. 4.0.3 will then work. 4.0.3 will NOT work if you did NOT uninstall 4.0.4. This may also fix the memtweakit issue.

As I said I've tried every bios version that gets released or leaked. I don't remember if I tried F3 but those old obsolete bioses didn't have working VF points. The person who told me this bug was fixed in X5 is a Gigabyte engineer but I don't know if he's with the BIOS team. He's the same person who sent me test bioses when I was helping gigabyte fix the very serious DVID overvoltage bugs on Z390 when switching to fixed mode (T0d and t1D from Z390 Master came from him).

A gigabyte rep told me that the 1T bug with dual rank dimms should be fixed in X5. I was not aware that no one had it yet. The bug is: on both 2018 (october sticker) and 2020 year (February sticker) Gskill 3200 CL14 2x16 GB Trident Z RGB (F4-3200C14-32GTZR) sticks, 1T command rate does not work at XMP on either set. (basic 3200 CL14, all auto timings). it just boot loops and resets after repeated fails at training. The 2020 sticks are much better clockers than the 2018 sticks at 2T.

X5 Bios is supposed to fix the problem with dual rank and 1T command rate (right now 1T completely fails to work even at stock XMP settings) 3200 CL14-32GTZR Gskill (2x16 GB) + 1T = boot loop.

Anyone have the X5 bios for the Z490 Aorus Master?

Please doublecheck the TXP setting in *gaming* before all of you use it. Check your 1% lows! One user tried using TXP 4, and his benchmark/latency scores went down nicely a few ms, but his 1% lows were worse and he tested it by toggling it on and off each reboot (Gigabyte board so it was already in the BIOS). So be sure to check it (assuming that some of you guys are actually gamers also).

Ok let me put this a completely different way. Maybe this will explain the awkwardness of what you're trying to ask a video gamer (me) who just plays videogames and who is not a hardware engineer. Let's say you set 1.45v in BIOS, Loadline calibration level 3. 1.1 mOhms of LLC. This is a perfectly safe setting. And 1.1 mOhms of LLC is intel default vdroop. Put 245 amps into the cpu that's 1450mv - (245 * 1.1) =1.180v. Clearly that's safe. If you want to "assume" 1.52v is "max VID", ignoring the "1.52v + 200mv" thingy, that would be 1520mv - (245 * 1.1)=1.250v. Now that's an ALL CORE LOAD. All 10 cores. So now you said 1 core load is 24.5 amps per core. 245 / 10. that makes sense. Now, what happens if you have a ONE CORE (2 thread) application that is putting 24.5 amps by itself, with NO other cores loaded? Then what??? At that 1.450v, the vdroop and load vcore will be: 1450mv - (24.5 * 1.1) =1.423v ! So according to the above, that "one" core with a 24 amp load on it will be getting a LOAD VCORE of 1.423v!! So that by logic should degrade that core pretty fast, shouldn't it? Because the total amps load is so low that the load vcore is going to be super high. Unless EACH CORE has its OWN VOLTAGE? But only on HEDT does each core have its own voltage rail because its supplied by VCCIN (1.8v). Do you see the position you put me in here?? I have absolutely NO idea or clue what I'm talking about anymore or any insider knowledge of how these chips work. I don't know the answers to these questions. I'm sorry.