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Tzk

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Everything posted by Tzk

  1. Yep, 3EG Rev3 seems to be based on 1/21. Interestingly Merlin ED and Hellfire 3EG Rev3 is nearly identical... Only a few values are different which improve system stability with multi 10 to 12.5. EDIT: 3EG Rev3 is identical with Merlin DFI 12/31. So i assume that Hellfire based his bios on DFI 12/31. There's only a tiny difference between DFI 1/21 and 12/31. I've yet to extract all romsips from DFI official and beta bioses though.
  2. At least from my side it's fairly simple: First, i only got Abit and Asus boards and second Hellfire seems to miss a changelog, so no clue what he did on the modbios he released... On LP B he used the 6/19 bios (and possibly also 6/19 romsips). That's what Trats ported to A7N8X in his 1008mod3 bios. I tried it and couldn't make it past 245Mhz 24/7 stable. With Merlin EBED (which is somewhat based on DFI 1/21 romsips) i'm able to reach >255MHz. So in simple terms: i didn't see any need to investigate the hellfire bioses I grew up clocking NF2 boards and was always limited by my knowledge. That's why i started pushing further as this is what socket A deserves ❤️
  3. I just tried combining the romsips to see if there is any effect, especially since i knew that Trats and Mantarays is clocking worse than Taipan on my asus... And i found that the limit indeed is lower on both. Haven't had a look at your tables up to now. If you need further data for the registers i can dump via wpcredit on my a7n8x dlx and a7n8x-x. Just tell me which registers you need. If you could make the newer settings work in Zenstates app that'd be awesome. I've had a brief look for A64 Tweaker and NF2 Tweaker sources, but it seems like CodeRed never released those to the public. I haven't had time to actually test a custom ISA rom, but that's my next goal: to get an ISA rom for DriveStrength, Slewrate, SuperBypass and DataScavengeRate working and on top of that read Cmos registers and set these settings depending on the cmos register content. That way i should get fully working bios options for those. The b-d-f registers itself should mostly consist of 4bit settings. So either the upper or lower half of the bytes are used for a single setting (except settings like Tras with >8 choices). Afaik the right half of settings on NF2 Tweaker are all 4bits. Tras, Trc, Trfc and the AGP/PCI latency should be 8bits. DriveStrength and Slewrate too. Not sure about SuperBypass and DataScavengedRate, but i'd guess 4bits. Again some code i found for option roms: https://gist.github.com/DruckiMcDruck/10d22bef2ac6ed1673ff15210c8aefb8 And here's a list with registers i found on different forums so far: https://gist.github.com/DruckiMcDruck/01174f3cd2bc2c1df6a7aa366060f304
  4. If Tref setting is available on NF2, then it is unknown. As we can control Alphatimings, i'd try to get Slewrate, Drive strength, SuperBypass and DataScavenged Rate working. Sadly NF2 Tweaker source isn't available and thus we have to manually find the registers. Afaik DFI has them in bios, so this might be a way to find them. Here's what i used for my comparison of romsips. I combined the blue first half with the orange 2nd half. Left is trats, middle is EBED and right is mantarays XT. Next up i'll swap the A7N8X and try my NF7. Maybe i can get it into a working state. And i'd like to try Merlins Bios, as up to now i mostly ran Mantarays XT.
  5. I did a quick comparison between my modded romsips. Base is Taipan EBED romsips + 3.19 BPL, CPC on. I then swapped the first half of the romsips to Trats 1008mod3 and D26 Mantarays XT while keeping the 2nd half of EBED. Setup is A7N8X Dlx, random Tbred B, 1x512mb TCCD (Geil Ultra-X) 3-4-4-8 and Memtest v5.01. I tested Test #7, as this seems to be the indicator if the chipset is stable or not. Vdd was 1.85V, Vdimm 2.7V. Results: EBED: 255Mhz pass, 260Mhz fail Trats: 250 pass, 255 fail MantaXT: 245 pass, 250 fail So it looks like the upper half alone gives me a 10Mhz increase in stable fsb when going from MantaXT to EBED. I'll post the exact romsips i used later.
  6. Well, we know all Timings in NF2 Tweaker if we a/b test them one after the other. Iirc most NF2 Tweaker Alphatimings are 4bits while for example Tras is 8bits. And if someone brave tests all available bios options on Abit and/or DFI we probably get most of them. This might also be of great help (ISA option rom sourcecode): http://www.xtremesystems.org/forums/showthread.php?109834-AMD-Athlon-64-DDR-ROM-Patcher Yes, you basically want to reverse the Soft-L12 mod. Most modbios have the 200Mhz tables copied to 133 and 166Mhz, so every cpu can reach high fsb. This makes sense for unlocked cpus but will make the performance on superlocked cpus suffer. If you got enough time you could even tweak a bios for like every 10Mhz of FSB (one for ~200Mhz, 210Mhz,...) to get maximum bandwith/efficiency for low-fsb cpus. Especially superlocked Cpus with high multi and low stock fsb might profit from this. Interesting observation that the top half of the table seems to allow for more/less fsb. I thought it's mainly the lower half which helps fsb. I built 3 romsip versions yesterday and might try max. FSB on them. I made D26 Mantarays XT upper half + EBED lower table; full EBED table and trats 1008mod3 upper + EBED lower half. Might be interesting to see how the max. fsb behaves on all of them, especially since my northbridge is definitely limiting my max. FSB. I need to increase Vdd to >1.8V to reach 255Mhz+, else i get errors in Memtest Test 7. I can't even get 2x512mb TCCD stable above 250MHz while 2x256mb Winbond is perfectly stable at 260MHz+.
  7. Well, for Slewrate, Drive Strength, SuperBypass and a few other registers we do know this, right? What i'm currently missing is the link between the bus-device-function adressing scheme and an adress like 08000C28Ch. Am i correct that this is a pci address in the pci address space? So converting this adress to binary leads to 32bits and those 32bits can be mapped to b-d-f adressing? Example: 08000C28Ch is ‭10000000000000001100001010001100‬ in binary. Let's split this into parts as described here: https://wiki.osdev.org/PCI#Configuration_Space_Access_Mechanism_.231 result: ‭1 0000000 00000000 1100 0010 10001100 this translates to: enable bit is set bus is 000 -> 00h device is 1100 -> 0Ch function is 0010 -> 02h register is 10001100 -> 8Ch As the address was 08000 C 2 8C h this result isn't unexpected, i guess. Or are you trying to inject code at an earlier stage of the boot procedure? So like manipulating Dram settings while the bios load the initial values?
  8. Ah well. I refused to use the newer modbin 2.04.03 because i disliked the new design. You can't see selections on the item tree anymore... That's why i stuck to 2.01.02. I also try to stay away from disassembling the system bios as it seems to be a mess of legacy (spaghetti) code plus some legacy limitations due to x86 architecture and several relocations of code during boot + decompression trickery. It's a mess... There's the source of an older award 4.51 bios somewhere on the internet, but we're on 6.0. So the general bios layout and structure will be similar but details will differ. Pinzakkos site is a great source for the bios structure though. EDIT: Here's what black.bin from blackmantarays does. It basically loads different registers and uses the different subroutines to push data through the PCI address- and dataport. All used subroutines look similar, but with variing ports. This looks like the examples shown on the PDF i linked, but uses subroutines to reduce code duplication.
  9. I just built some custom romsips with the upper half of D26 Mantarays XT, Taipan EBED and Trats 1008mod3 while keeping the lower half of Taipan EBED. B0D0F0, F2, F3 and F4 differ while B0D0F1 and F5 stay the same. However on B0D0F4 the only difference i get is A4h and A5h, everything else is identical. So no different Slewrate or DriveStrength. Aren't these repeating values below the romsip just some padding bytes or placeholders? Regarding the other tables: DFI got 10 tables while all other boards got 6. Maybe the tables inside the decompression block are used as defaults during boot or when cmos defaults are loaded? I know about the modbin method, but on winxp i can't overwrite the original.bin while modbin is open. You keep modbin open and modify original.bin while modbin is still running in the background? I'll have a look at the Blackmantarays bios, thanks for pointing that out! EDIT: Looks like the black.bin patches some pci registers as it writes to 0xcf8. TicTac might use this for the Cpu Disconnect Patch which is mentionen in the readme. If i got it right he writes to Cmos register 0C, 48 and 6C. Still might be a good idea to just modify this for my custom code.
  10. I already made a table to compare these side by side but didn't draw any conclusions. I thought that these might store subtimings/alphatimings, drive strength or slewrate. However i didn't build different romsip combinations to test this. If you want to test this, you could swap only the upper half and check registers with wpcredit to see if for example the drive strength changed. Here's what Trats 1008mod3, Merlin ED and D26 MantaXT looks like. I marked the difference in yellow. Note that using the lower table gives me a lot of extra FSB on the Merlin bios vs. Trats (260 vs. 245Mhz). So the magic must happen in the upper half of the romsip table at offset 100h to 180h. I didn't use a multi for testing which is affected by the 1510 vs. 1518 setting (multi 10 to 12.5 i guess). Now i should probably use a single lower half table and combine it with the different upper half tables... And then dump chipset registers with WPCRedit i guess...
  11. Technically yes, but the asus hides vcore selections depending on the default vcore of the cpu and/or cpu type. Basically my XPm has 1.45-1.825V in bios, while a regular Tbred has 1.65 to 1.85V. All other settings get hidden by the bios. Asus is way more restrictive than Abit on Vcore... no >1.85V options. But at least you got Vdimm fed off 5V, so you can mod Vdimm to >3.6V. I might try giving the vcore setting new options in _EN_CODE.bin, maybe that does the trick. I already did this for my "new" items and it worked great.
  12. How was the "dead" nf7 and an7 behaving? I currently got my best nf7 bricked. It boots, but just freezes after ~5mins, even if i'm just in bios. If i wait a bit i can repeat this. Regarding the selection, have a look at the PDF i linked, page 214. Swapping bios items is the easiest method i know of to get the setting back. Downside is that you need to sacrifice another item to make it work. I also got a similar issue right now. Asus limits the selectable vcore depending on CPU type on A7N8X... XPm doesn't have the 1.85V choice, only 1.825. Regular XPs can't use below 1.65V. And i feel somewhat offended by this behaviour.
  13. That is exactly where i got my information from. Tictac, Polygon and some other guys wrote a lot of guides on rebels haven forums about this. Tictac hacked option roms to load Uref values on NF4 boards, also including added items in award bios, hacking option roms to load custom code etc. I uploaded a PDF to the bierbude server, just in case you haven't got it yet: http://bierbude.spdns.org:2302/USER UPLOADS/Tzk/ Option roms seem to have a far jump or call at the beginning, thus the easiest way is to manipulate that to a custom jump, insert custom code and do the original jump/call at the end of the custom code. This way you don't have to mess with the bios too much and you can insert a lot of code, as long as there's sufficient space inside the option rom This is explained at page 115 of the PDF. --- I noticed that memtest uses the 55AA option rom header but couldn't figure out how i'd insert the vendor and device ID into it to make it load upon boot. That's why i stopped investigating. At least for now. But if you can make plop work, you probably also can make memtest work.
  14. PN sent for Cbrom and modbin. You can extract modules with cbrom, i use AWDbedit though. No, i couldn't add a working Memtest module but didn't investigate further. I noticed that Biostar (P965) and DFI (NF4 Ultra-D) split Memtest in two parts: memsetup.rom and memtest.rom. These two parts together look like the usual memtest bootable binary. I also noticed that they use 55AAh in said binary (that's the PCI option rom identifier). Maybe memsetup.rom must set the something before memtest is booted. I've tried to just replace awdflash.exe with memtest.exe, but that (obviously) didn't work. I haven't tried to replace a pci option rom with memtest yet (for ex. PXE boot). That's the next step i might try. But before that i'll try to hook/hack into the existing option rom to make my bios mods functional. Here's the start of a bootable memtest file. The content of the red box is in memsetup.bin in the DFI and Biostar bios. The green box isn't used in bios-memtest. blue is the pci option rom identifier (55AAh). The actual memtest program starts way below this, indicated by the zeros at the bottom, that is in memtest.bin on DFI and biostar. I'm not sure what spectrum.exe on DFI NF2 bios does. Just wondered why it's there.
  15. As always: !!!! THIS BIOS IS UNTESTED, MAKE SURE YOU CAN RECOVER YOUR BOARD IN CASE THIS BIOS IS FAULTY !!! There you go, EB ED romsips integrated into the bios mr.scott uploaded above. Make sure you can hotflash or otherwise recover the bios just in case i messed up EDIT: I removed the EBED test bios. I accidentally included the system module from Merlins Discovery 0.1 bios instead of 0.3. See later posts for updated files. Updated files here:
  16. Is there any difference between the Disco 0.3 Mr.Scott linked and the version you're looking for besides the EB and EBED difference? Or in other words: Would a modded EB bios with EBED romsips work for you? This is the difference between EB and EBED. One table is Cpu Interface on, the other is Cpu Interface off. Every yellow mark is for one cpu multi setting. So depending on your desired multi you may literally see no difference between these two bios versions. The settings are stored like this for the different cpu multis: 11.0 11.5 12.0 12.5 5.0 5.5 6.0 6.5 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 So we can conclude that the following multi settings are different between EB and EBED (from top to bottom): 11x - 11.5x - 12x - 12.5x - 6x - 8x - 10x and 10.5x
  17. WPCRedit works on drive strength and slewrate? nice. I've only read about Tictac having issues with freezes and (up to now) didn't bother to try for myself. You set all 6 settings one after another for DS and slewrate? --- Yes, i use modbin6 2.01.02 for menu editing and cbrom 1.98 for bios module adding/removing. However you'll need to tinker with hexeditors when you want to have new selectable options on bios items, you can't do that through modbin. I found a great PDF with posts by polygon originally made on rebels haven forums (sadly whole forums doesn't exist anymore) about the structure and editing of Award bioses. It even explains how you'd add new items, but only for bioses which got an item.bin module. Sadly the a7n8x bioses are too old and store the item.bin content directly inside the system module mixed with code. I tried to add new options but every try (and i tried like a dozen times) left me with a bricked bios. Here's how a single item looks like in system.bin (marked in blue). If i just insert another item between the blue mark and the "press enter" the bios won't boot. Thus i suspect that the code makred in pink does something and any addition above it is either causing problems or i need to add something somewhere else.
  18. What do you mean by changing registers? In bios or after OS boot? I can't remember if AN7 or NF7 allowed for DS and slewrate adjustment in bios... At least Asus doesn't which is hat got me into hacking the bios I got two NF7 but the better one (250MHz+) just randomly freezes after a few minutes, even when just in bios... I also wondered where these settings are stored in the bios... Could it be that they're saved inside the romsips? Haven't tested different romsips myself to verify this up to now. But i notices a difference between official 1007 and my EBED bios on A7N8X Dlx. Regarding the DS and slewrate setting: I remember that TCCDs liked rather weak DS and Winbond maxed out when you gave them everything you had on NF4 boards. Not sure about slewrate.
  19. Sure! I use this model from South Korea: https://www.ebay.de/itm/NANO-USB-Programmer-for-PC-M-B-BIOS-repairing-with-Economic-shipping/271313593344 And i bought additinal 4mbit bios chips from china: https://www.ebay.de/itm/5-PCS-PM49FL004T-33JCE-PLCC32-PM49FL004-Flash-Memory/121360397788 Note that some a7n8x got 2mbit (256kb) chips and some got 4mbit (512kb) chips. My A7N8X Deluxe v2.0 uses 4mbit, afaik the -E Deluxe too. But A7N8X v1.x and -X should use 2mbit chips. Also note that the flasher works fine with win10 64bit, but it will set your system to "testmode" because the driver isn't digitally signed. And last but not least, if you intend to test a lot of bios versions, buy a plcc32 chip extractor. It'll make your life so much easier
  20. This is how far i've got up to now. Moving items around in bios is fairly easy, but now they also write their settings to the CMOS registers (i use 75h to 77h on a7n8x dlx). Next i'll try to inject code into one of the bios modules... Currently the cmos registers are set but there's no other effect - so no changed ram settings right now. I also couldn't manage to add new unused items to bios. So for now i can only make use of the 5 items which weren't in use on the stock bios.
  21. I'm still digging through the bios to add/change options. Adding custom labels works now, but i need to find free cmos registers i can store my settings in. I found a screenshot of "ACE - Advanced Cmos Editor" but can't seem to find this tool anywhere. Do you guys know of a similar tool which shows the used/unused cmos registers?! The other option is to extract all settings from system.bin (~210 items) and to manually build this table. EDIT: Looks like i finally found a tool which can do this... R/W Everything v1.7. If you select IO Index/Data (Index Port 0074 + Data Port 0075), then you get the cmos data. Whoah.
  22. This should at least work for the Subtimings as you can set these via NF2 Tweaker in Windows. Regarding the other settings: no clue. although i remember that you'd have to set multiple registers at the same time, else the system would freeze. But yeah, if we're going down this route it might be neccessary to remove the default routine and replace it with custom code. If i can't find a way to add new items this whole discussion is pointless though.
  23. Afaik setting Slew Rate, Drive strength, Super Bypass and maybe Data scavenged rate in windows freezes the system, no? I'm fully aware that you need to somehow trick the bios to make it execute custom code which you can put for example in a pci option rom...
  24. Basically whatever you want. By Default they're just items shown in bios without a function. You need to add the items, add the selectable options and then modify the code of some bios module to actually do something. You can for example modify any chipset register or even run custom code while booting. So it might be possible to change Alphatimings, Drive Strength etc. It must somehow be possible because DFI does it on LP B and Infinity. However this is a very difficult task as it involves assembler programming and reverse engineering. And i'm not a programmer... I'm currently trying to do this step by step, but still i might fail. The problem is that there's only 5 unused bios items inside the A7N8X bios. However you got about 10 settings in NF2 Tweaker plus Drive Strength, Slew Rate, Data Scavenged Rate and Super Bypass. So this equals at least 14 settings. So i need another 9 items to be able to have them all inside bios. You could reuse other bios items, however i don't want to remove 9 (probably important) settings from bios. DFI has about 250 items in bios while A7N8X only has 213 and -E DLX has 211. So there must be a way to have another 15 settings... As the difference between A7N8X and -E DLX is rather small, i'm comparing these to find the differences of the 2 settings and how Asus put them into the A7N8X bios. No clue if this is of any help, but that's the best idea i currently got.
  25. I'm currently trying to add new items to the a7n8x bios... There's a great guide by Polygon of the (now gone) Rebel Haven forums called "Practical Bios editing", but sadly i can't seem to replicate the steps he took. It looks like there's two types of Award v6.00 bioses: a) with _item.bin b) without _item.bin. In case b) the Bios settings are stored directly in the 128kb system bios module inside the bios and mixed with something that looks like assembler (?!). Whenever i change something to add another item, modbin won't read the bios anymore. My A7N8X bios has got some unsused settings which i can use, but there's only 5 of them and i need like another 10 more... Has one of you managed to successfully add new items to a bios without _item.bin?
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