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Tzk last won the day on July 2

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  1. Congrats, that should be the current FSB WR on Socket A. Also looks like 300 is just a limit in bios/software, not chipset. NICE.
  2. All this wouldn't be possible without the overclocking elders (OskarWu, Tictac, Polygon) which did the groundwork for this. Also the openness of recent socket 462 overclocking and sharing all findings and infos was key. So a true team effort And let's not forget about the new NF2 Xtreme tweaker made by @I.nfraR.ed. His work makes this a lot easier to clock NF2 and set timings in Win. I also believe there is more to gain, especially on 1:1 dualchannel. I'm still stuck at 263Mhz for 32M runs.
  3. Been there, done that. 256mb BT-D43 1:1: https://hwbot.org/submission/4794219_tzk_reference_frequency_a7n8x_deluxe_(rev2.0)_273.48_mhz/ 256mb DT-D43 and BT-D43 run exceptionally well on the A7N8X and NF2 in general. My best stick of BT-D43 is mostly done at 273Mhz, though. DT-D43 doesn't clock above ~255Mhz 32M. BT-D43 runs 263Mhz 32M in Dualchannel which probably is the chipset limit of my board.
  4. Congrats, huge achievement. Especially on ambient cooling. The big question is: can the NF2 be clocked over 300Mhz?
  5. Not sure i can improve on this. I can't boot any Mhz higher (currently ~220Mhz) with this ram divider and work my way up to 290. Maybe i'm not hitting the limit of the board, but falling out of the FSB window. NF2 doesn't like raising FSB via clockgen too much Already tried using 1.9V Vdd instead of 1.85V and that didn't yield a single Mhz extra.
  6. @exaberries The board is fully recapped with poly caps. I used 2x Panasonic FR 3300uF 16V for the 12V rail, 5x 2700uF 4V Kemet polys for the cpu and a bunch of other caps for the whole board. The full list including the positions is here: https://www.hardwareluxx.de/community/threads/der-nostalgiedeluxx-bastelthread.1224414/page-63#post-28112691 I also soldered an additional 4pin like Terraraptor did plus i run a wire from the 12v pin on the 20pin connector to the cpu VRM. Here's how the board currently looks like:
  7. Bump, digging with a golden shovel after 9 years... Someone on the HWBot discord mentioned this neat tool. Sadly the issue with winxp is still persistent... Is there any hope that either @W1zzard fixes this or maybe the source is released so someone else can have a look at fixing this? Reading the Microsoft docs on this, it seems that compiling it against PSAPI v1 instead of v2 should be enough? https://docs.microsoft.com/de-de/windows/win32/api/psapi/nf-psapi-getprocessimagefilenamew
  8. 😲 Seriously? That's the one thing i never tried in all those years... I usually just kept what the board used as default for synced FSB:Dram. Might be interesting to dump the chipset registers and to see if there are differences.
  9. So i tested a few more cpus. My current conclusions about BCRC are: if the cpu has a minor revision of 2 or 11, then it is reported as multi locked if the cpu has a minor revision of 12 or 15, then it is reported as multi unlocked minor revision 11 is reported as Thorton w/ 512K, all other minors are reported as Barton Stepping is just a guess and mostly AQYFA or unknown Now, i added Antinomy's cpus to my list and sorted them by minor revision and week. Revision 2 has two ranges with a gap in them: 0337 - 0349 (?) and 0405 - 0411 (locked) Revision 11 was made from 0342 to 0512 (locked) Revision 12 also has two ranges with gap: 0327 - 0332 (unlocked) and 0403 - 0407 (locked) Revision 15 seems to be the oldest: 0318 - 0319 (unlocked) So i believe the timeline of the revisions is: 15 -> 12 -> 2 -> 12/2 -> 11 On german Hardwareluxx forums there is a user which states that AMD changed something inside the cpu die which makes them clock a lot better. That's why the mobiles from 0351 onwards clock so much better than older Bartons. I believe that it's the change to minor revision 11 which is to "blame" for this, although we need more cpus/data to prove this. We also need more cpus to see of the gap in revision 12 and 2 is real...
  10. Just a thought: Wouldn't it be better if we could open that info box with a button inside the tweaker? So we don't have to close it on every tweaker launch if we want to "just" change timings. Also the frequency and FSB display is currently broken on A7N8X, right? Tweaker reports 151Mhz and Multi 11 while Cpu-Z shows the actual values (133 + 12.5x). Besides that the MSR values between BCRC and Tweaker match, well done!
  11. Perfect. So now we can use BCRC and your tweaker to read the values. Will retest the above mentioned cpus. @Antinomy A question regarding the forums and its editor: Is there a possibility to install a plugin for the WYSIWYG editor to include tables? The table above was just copy&paste from excel, but i can't change the table width... Not sure how you did it in your post.
  12. @Antinomy and @I.nfraR.ed shared their thoughts about superlocked cpus and cpu registers (MSR). Maybe we can identify superlocked cpus like this... They also mentioned a tool called Barton CRC (BCRC.exe). So i grabbed a few cpus and here's the result so far. Example screenshot of BCRC output: Here's the result which BCRC reported. The first columns is what i read from the cpu sticker (orange), latter ones are output of BCRC (blue). My conclusion so far is that the minor rev is rather random and the superlock plus the Crystal marker seems to be a more or less random guess. Nr Cpu Rating Stepping week Stepping ED Value CPUID Processor Code Major Minor Type Crystal Marker 11 Athlon XP 2600 AQZFA 0349 TPMW 2306h 06A0h Barton 0 2 locked AQYFA 12 Athlon XP 2600 AQXDA 0318 MPMW 2319h 06A0h Barton 0 15 unlocked unknown 13 Athlon XP 2600 AQXEA 0404 TPMW 2316h 06A0h Barton 0 12 unlocked unknown 15 Athlon XP 2600 AQYHA 0401 UPMW 2315h 06A0h Thorton w/512K 0 11 locked AQYFA 16 Athlon XP 2600 AQXEA 0403 WPMW 2316h 06A0h Barton 0 12 unlocked unknown 17 Athlon XP 2800 AQYHA 0409 SPMW 2315h 06A0h Thorton w/512K 0 11 locked AQYFA
  13. When i started looking into romsip modding i found this post by TicTac on pcper forums. See attached screenshot for content. So yes, these are indeed multi specific settings... This made me test my FSB stability at multi 7 or 7.5. If it is stable on these multis, then it'll run on any multi. However he didn't state what these settings are actually controlling. If we can find this out (also for the upper half of the romsips), then we might be able to push the fsb further. We also hit a hard FSB wall at about 263MHz right now, on the german Hardwareluxx Forums we got about 4 or 5 boards which won't pass 32M above 263Mhz, no matter what you do. Vdd, Vcore, Multi doesn't matter, some boards do even freeze when trying to set 264/265 MHz. No clue what causes this, might be some peripheral controller or even the chipset itself acting up. broken link: https://pcper.com/forums/?346001-ROMSIP-Table-Mod-Guide#post3100010
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