Jump to content

Antinomy

Crew
  • Joined

  • Last visited

Everything posted by Antinomy

  1. Antinomy replied to Antinomy's post in a topic in Old School
    I've been playing with s478 so here's something interesting. My BIOS does work with P4P800 (PCB rev 1.02) and P4P800 SE (PCB rev. 2.00). Next thing I wanted to check is PAT since I had 875 and 865 boards using the exactly same BIOS. As some of you know, Asus managed to enable PAT on 865 boards. This has been done using FSB133 strap with 1:1 divider. So, one thing to know - PAT can be enabled partially and fully. Memset doesn't show the difference so it's useless. Another option that Asus has is performance mode [auto/turbo] that tightens subtimings and enhances latency. Both PAT (performance acceleration mode is Asus BIOS) and performance mode have a major impact on memory latency and less on memory throughput. So here's some AIDA tests: Asus P4C800-E, P4P800 SE, Pentium 4 3.0E, 2*512 Winbond 2-2-2-5 1T, 1:1 strap 200, FSB 200 P4C800-E, PAT, auto 6296/4273/5031/80.7 P4C800-E, PAT, turbo 6293/4274/5031/70.6 P4P800 SE, no PAT, auto 6282/4273/4862/102.6 P4P800 SE, partial PAT, auto 6294/4273/5007/88.7 P4P800 SE, partial PAT, turbo 6293/4273/5018/80.6 So, things to consider here - 875 and 865 are different. PAT, even partial does work both on 865 and 875. Gain from partial PAT is less than from full PAT. Now time for some magic. P4P800 SE, 1:1 strap 200, you can see partial PAT. Now we boot with P4P800 SE, 1:1 strap 133 on FSB200: We can see fully enabled PAT and latency that clearly confirms this. But this info wasn't new. P4P800 SE, 5:4 strap 200, FSB200: P4P800 SE, 5:4 strap 166, FSB200 We can see fully enabled PAT with 5:4! So after some testing and double-checking on P4P800 (rev. 1.02) I can say this: 865PE can use fully enabled PAT on all straps and dividers except strap 200 (1:1, 5:4, 3:2). So PAT works on 1:1 strap 133, 5:4 strap 166, 3:4 and 4:5. In these modes 865PE will be fully equivalent to 875P.
  2. Wow, excellent work! Finally you're growing up
  3. Thanks, finally could hit the 200FSB barrier. Unfortunately with current revision, it's useless hwboints-wise ?
  4. Antinomy replied to havli's post in a topic in Support
    The manual states ESP 6000 and C3 800. First with passive cooling, second with active (common solution for VIA boards). Taking a look at the photos we can see the passive solution (it has a different heatsink than the active one even without the fan). Nice find with 5000 and 10K though! Not to mention that VIA C3 1266 doesn't seem to exist at all.
  5. Indeed. Renamed to P4G8X / Deluxe A bit different - P4P800/P4C800 have compatible BIOSes. As for P4G8X it's the same BIOS file for both versions. Hence they're the same for any software. The only differences are onboard peripherals.
  6. Antinomy replied to havli's post in a topic in Support
    No. SiS have same GPUs for mobile/desktop parts. Google.
  7. Antinomy replied to havli's post in a topic in Support
    No. No.
  8. I'm in this for the last two years and I agree, it's another world. It's definitely not nice, it's tough, but this kind of hardcore is what makes it so interesting. And drives you mad sometimes IGPU memory IS main memory, there's no other onboard. As for frequency, not necessary, most ATI chips were truly asynchronous so talks about divider in this case is sort of formality, nothing more.
  9. Antinomy replied to liq_met's post in a topic in Support
  10. Antinomy replied to liq_met's post in a topic in Support
    Where?
  11. Antinomy replied to liq_met's post in a topic in Support
    It's not integrated, it's onboard. Integrated means GPU integrated into chipset or CPU unlike usual discrete GPU chips.
  12. It's not mostly the PLL that is bugged, it's the system timer. But on 1.03 the fluctuations were wild like down to 4-5MHz FSB. This began after a certain version of CPU-Z, I think Gumanoid was using one that wasn't yet affected. Got broken later.
  13. Yeah, that's the one that gives most terrible fluctuations. I've reminded Franck of this issue.
  14. O.K. Looks like I got the test build where this was fixed, I checked it but Franck didn't apply it to release versions. I'll remind him of this issue. If your P5A rev. 1.03 with Phaselink PLL? Or is it the newer ICS version?