Don_Dan

This score was made in August 2008, exactly around the time when this thread was posted. However, your score was submitted to HWbot not even 5 months ago... They WILL remove every score made with the 3:5 divider cause I'm reporting them when I see them.

That's a crazy frequency! Nice one!

Great score HC!

Congrats for 50k!

Well done!

3:5 on 400 strap is 2:3 in reality, kawaboy.

Good run, I'll keep my fingers crossed for 50k!

Well done, I wasn't expecting 700MHz that early in the competition. @mr.paco: The T2RS is a DDR2 mainboard, CPU-Z has trouble reading the correct memory type on some boards, the T3RS is the DDR3 board. Older versions were also showing PC2-... under memory type, I don't know why CPU-Z stopped doing so.

Good start, almost the same clocks you reached on Lynnfield!

There we go again! Nice one!

Yes.

I already sent a PM regarding stage 2 to Massman three days ago, but I'll repost it in public. I had a hard time believing all the CL4 scores that have been posted, so I checked some datasheets from both Elpida and Micron: Micron D9GTR Datasheet, page 111: CAS Latency (CL): The CL is defined by MR0[6:4], as shown in Figure 53 on page 109. CAS latency is the delay, in clock cycles, between the internal READ command and the availability of the first bit of output data. The CL can be set to 5, 6, 7, 8, 9, or 10. DDR3 SDRAM do not support half-clock latencies. Also, right at the beginning it says: • CAS (READ) latency (CL): 5, 6, 7, 8, 9, 10, or 11 • POSTED CAS ADDITIVE latency (AL): 0, CL - 1, CL - 2 • CAS (WRITE) latency (CWL): 5, 6, 7, 8, based on tCK Then I checked Elpida's datasheets, I think the correct MGH-E datasheet is not available, so I had a look at the one for EDJ1108BASE in general. Right at the beginning it says: • /CAS Latency (CL): 5, 6, 7, 8, 9, 10, 11 • /CAS Write Latency (CWL): 5, 6, 7, 8 Seems like CL4 is not supported by DDR3 at all and the boards are running at some other CAS Latency. I know some guys think those clocks are real, but please show me CL5 at those clocks, it should be easy, right? I heard some guys are also hoping for CL2 on DDR2, here's an excerpt from a Micron DDR2 datasheet: CAS Latency (CL): The CAS latency (CL) is defined by bits M4–M6, as shown in Figure 36 (page 79). CL is the delay, in clock cycles, between the registration of a READ command and the availability of the first bit of output data. The CL can be set to 3, 4, 5, 6, or 7 clocks, depending on the speed grade option being used. DDR2 SDRAM does not support any half-clock latencies. Reserved states should not be used as an unknown operation otherwise incompatibility with future versions may result.

Great job!

Nice score!

Nice clocks! Please run some benchmarks as well!

Finally 12k, well done!

Nice scores!

Well done!

Welcome! Keep pushing it!

Awesome score Steve!

Nice run!

Nice run!

Well done!

What do you mean? He has given the P/N under memory details, and it can also be found in the Memory tab of CPU-Z under P/N.

Some more pots by Otterauge: Xtreme Edition, Xtrem ONE, (Rev.) X1 and X2, Rev. 02 and Rev. 01, all for CPU. NB Kühler = full copper NB cooling. Multi GPU Kühler for GPUs.