ARandomOWl - DDR3 SDRAM @ 924.5MHz - 924.5 MHz Memory Clock

[I.nfraR.ed]

Nice, no chance for DDR2 on this stage.

[Massman]

Bugged ?

[ARandomOWL]

How is it bugged? I have validations at every 1MHz FSB before this back to 600. Bugged divider is 5:8 on 400 strap I believe. I am using 266 strap with 2:3 divider. I get same RAM MHz on 266 strap with higher divider (think it's 5:8).

[TaPaKaH]

D9GTR, right ?

[Massman]

CL4 at that frequency is mental

[I.nfraR.ed]

Well, DDR3 will handle CL4, CL6, CL8 and CL10 stages, DDR2 - CL2 stage. DDR is out of the game, I suppose.

[ARandomOWL]

D9GTR, right ?

 

It is indeed. Cellshock 1800 8-7-6-21