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ARandomOWl - DDR3 SDRAM @ 924.5MHz - 924.5 MHz Memory Clock

I.nfraR.ed
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How is it bugged? I have validations at every 1MHz FSB before this back to 600. Bugged divider is 5:8 on 400 strap I believe. I am using 266 strap with 2:3 divider. I get same RAM MHz on 266 strap with higher divider (think it's 5:8).

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    Well, DDR3 will handle CL4, CL6, CL8 and CL10 stages, DDR2 - CL2 stage. DDR is out of the game, I suppose.

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