I.nfraR.ed Posted October 4, 2011 Share Posted October 4, 2011 Nice, no chance for DDR2 on this stage. Quote Link to comment Share on other sites More sharing options...
Massman Posted October 4, 2011 Share Posted October 4, 2011 Bugged ? Quote Link to comment Share on other sites More sharing options...
ARandomOWL Posted October 4, 2011 Share Posted October 4, 2011 How is it bugged? I have validations at every 1MHz FSB before this back to 600. Bugged divider is 5:8 on 400 strap I believe. I am using 266 strap with 2:3 divider. I get same RAM MHz on 266 strap with higher divider (think it's 5:8). Quote Link to comment Share on other sites More sharing options...
TaPaKaH Posted October 4, 2011 Share Posted October 4, 2011 D9GTR, right ? Quote Link to comment Share on other sites More sharing options...
Massman Posted October 4, 2011 Share Posted October 4, 2011 CL4 at that frequency is mental Quote Link to comment Share on other sites More sharing options...
I.nfraR.ed Posted October 4, 2011 Author Share Posted October 4, 2011 Well, DDR3 will handle CL4, CL6, CL8 and CL10 stages, DDR2 - CL2 stage. DDR is out of the game, I suppose. Quote Link to comment Share on other sites More sharing options...
ARandomOWL Posted October 4, 2011 Share Posted October 4, 2011 D9GTR, right ? It is indeed. Cellshock 1800 8-7-6-21 Quote Link to comment Share on other sites More sharing options...
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