ground

with these boards you can literally grab some dead 1366 chips, throw them in, pass post once and they will work again in other boards as well. I've done it 2-3 times with DOA Bloomfield chips (I still have no idea how people manage to kill bloomfield), Luumi managed with a couple 32nm ES chips as well iirc. The chips seemed to behave perfectly fine afterwards (had one i7 920 that did 5.3 multicore but still BCLK limited from this trick, core felt good for 5500+ given behavior)

Woah! Thats a proper record! Shows the possibilities with these new tools that have been appearing last couple years for older platforms. Keep pushing!

Mem is slow, with proper mem could do ~6:14 easy at those clocks

could just as well be BABG.

prepare to bin anywhere from 200 to 2000 CPUs.

They recently started allowing old version again

if looking at the global ranking on the right edge of the screen, intuitively I'd expect the lower link - listing the result - to lead to the result. It leads to DDR5 rankings though. Given that the actual result is linked on the right edge of the same table anyways, wouldn't it make more sense to have the link only say "DDR5 SDRAM"?

Tapakah was visiting too lmao

I'm not aware of kingpin doing that, but earlier this year TAGG, Shaggy and I went for it with our collection of dead hypers. https://imgur.com/a/hyper-per-ic-binning-repair-session-feat-tagg-shaggysvk-ground-VZCouIh

disallow optimal platforms? No Haswell for DDR3, no Rocketlake for DDR4, no Raptorlake for DDR5 maybe?

have we had 1151 - 4 different generations? eg 6th, 7th, 8th and 9th gen? Cezanne only seems fine, though the quad cores are a bit of a pain being oem only, maybe make it APUs only? Gives cezanne the edge, but allows 4300G or earlier APUs to play since those quads are more available

E8600/x5260/x5270 QX9750 behind those, other quads have mediocre OC potential due to fsb limitations on them or due to c1 cores.

Sounds fun, but with 4GHz limited to max 1333MHz mem (unless you allow uncore > core which I would advise against), so maybe 4500 limit? That should allow *any* viable mem config given the IMCs. Edit: perhaps unique mem IC, though that would be pretty difficult to enforce.

I wasn't even aware the DFI x58 boards could run gulftown

Missing the literal pile of Single Stages lol