Posted October 25, 201212 yr Hey all, So I had the opportunity to get some data from a bunch of A10-5800K CPUs. The CPUs were testing both on air with the TCI K² application and on LN2 (two bins). - Bin #1 = 1.85V, load bios profile and up multiplier - Bin #2 = max voltage, max clock Test Setup - A10-5800K - GIGABYTE FXA85X-UP4 (bios F2, F3i) - HD 7760D - Der8auer Fusion rev3 - Kingpin Dragon F1 Gemini 2.0 (Fast base) How to bin - install CPU - open the TCI K² application - go to CPU info - note down leakage info and VID Basically, you need a CPU that is - Ultra High Leakage - VID lower than 1.30V My results I tested two batches: - 1219PNN: retail silicon, same I used for the HWBOT Testlab #1 - 1239PGT: 'special' bin So far, the 1.2875V bin looks the most promising ... should try that one on LN2 I think . Just my 2c.
November 2, 201212 yr Author Hicookie already did [hwbot=2323708]submission[/hwbot] Fyi - now trying to figure out how to find good IGP chips. It's not just about low VID there ...
November 2, 201212 yr Nice! I will check my "6.9" chips how good they are according to K2 application
November 24, 201212 yr From my playing around with the trinitys so far it looks like you need a mix of mid to low NB voltages, along with good IMC strength. Though i really haven't put enough chips through my setups yet to build a reliable dataset to prove this. But its a starting point atleast. Since the best IGP numbers generally come from as high of NB frequency as possible.
December 17, 201212 yr thanks ~ ^^ may i have a 1 question? how about max voltage (trinity) for stable oc (usually using) ------------------------------------------------------------- now i use A10 5800K 4.6G (1.45/load LLC 1.472) /Tem max 60C(liquid) prime small mode 8H pass Edited December 17, 201212 yr by geforcelove
December 17, 201212 yr depends at cooling...high air or allinone watter, you can set 1.55V. But there is a problem, you can have CPU part stable OK, but iGPU part not (if overclocked both parts in APU). With higher GPU clocks is harder to get more MHz at DRAM. Big stress for IMC.
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