Crew Antinomy Posted June 23, 2021 Crew Share Posted June 23, 2021 (edited) Hello, I'd like to separate some in-depth research considering sA that started in this thread: https://community.hwbot.org/topic/187148-a7n8x-e-deluxe-as-an-alternative-for-socket-462/ I'd like to discuss some sA and NF2 specific mods to: Make instructions for beginners Investigate other BIOS mods Make some progress if possible I'd like to investigate the work done by gurus like Merlin, tictac and many others, take the best from them and maybe move ahead. It would be very nice to get over 250FSB by tuning system registers and check how it's done. I'll start with some known mods and would like those familiar with ( @Mr.Scott ,@I.nfraR.ed, @digitalbath, @Tzk, @Strunkenbold, @TerraRaptor) to check in and correct if I'm wrong: BPL mod (also NVMM in later versions) - memory init routine from NV. Newer versions are better (up to 3.19?), latest are sometimes incompatible. CPC off (=CR 2T) seems to be modded in BPL. ROMSIP - a set of tables (CPU interface on/off, and for 100/133/166/200 FSB) with CPU and chipset related settings. Influence stability, overclocking, performance. soft-L12 - a mod that acts as BSEL, forcing BIOS to implement FSB200 settings even on FSB133 CPUs. Most mod BIOSes have it, add stability on high bus speeds. modified alpha-timings (can be set using the new NF2 tweaker from Infrared) options ROMs with performance tweaks (3D-fire for example - modified chipset registers?) changed some northbridge registers (S2K control probe limit, XCAARB_RD/WRCOUNT, DQSEN_PULL_B, Auto Refresh Cycle Time, Read-to-Read Command Latency, Pre-charge All Command ) (seen on Asus A7N8X dlx mod BIOS) Please, stay to the topic, don't discuss CPU binning, memory, voltmods and other things. BIOS mods and how they affect the system is the primary goal. Do not discuss cosmetics and general BIOS techniques like opROM update, unlocking menus and so on. I believe we all know how this is done (or it can be discussed in a different topic) so we can focus on advanced stuff. Infrared's Discord channel about Socket A: https://discord.gg/YKHvEt6xct Summary of nf2 registers: https://docs.google.com/spreadsheets/d/1ZDST3XGq0oE7YtQxAME29RtopA8QcePCaHa2NBRHaB8/edit#gid=0 Edited July 1, 2021 by Antinomy 6 3 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 23, 2021 Author Crew Share Posted June 23, 2021 I'll start myself with the ROMsips. I believe that the table consists of two parts - the first part is chipset-related. The second part is CPU-related. The main problem was that I've been trying to match multipliers to CPU part of the table. Then I've remembered this part. And I've understood that FID isn't endoded in ROMSIP. Instead, FID itself is a link to ROMSIP. Let's look at FID table: So, all multipliers are represented by 16 values that are used by SIP (serial initialization protocol, which is quite advanced). And now take a look at the CPU part of ROMSIP: Do you see this? Multis 11-12,5 (and all higher) have same last two bytes, then 5x and 5.5x are different. The first ROMSIP uses different settings for 6x, 6.5x but the second one has same settings as 5x, 5.5x. So these do look like CPU settings. I believe some of them are delays that are programmed during SIP packet. Might be lame, but I didn't see this info before. 3 Quote Link to comment Share on other sites More sharing options...
TerraRaptor Posted June 23, 2021 Share Posted June 23, 2021 I was expecting the last two registers (like 16 18 or 26 18) to be drive strengths for receiver/transmitter aka cpu side and NB side. I have killed two cpus when experimenting with that part of SIP, though should re-validate it by killing another cpu setting it FF FF. 2 2 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 24, 2021 Author Crew Share Posted June 24, 2021 (edited) 16 hours ago, TerraRaptor said: I was expecting the last two registers (like 16 18 or 26 18) to be drive strengths for receiver/transmitter aka cpu side and NB side. Were you able to set any combinations of values? Seems like they're tied together and you can't set random numbers. Maybe it's my setup. OK, the last three bytes of each multiplier in CPU part of ROMSIP are connected to b0d0f0 rE4-E7. Whice is S2K CONTROL 1 REGISTER. It configures timings of S2K (EV6) bus. But you can't change any bit in the ROMSIP, they are connected somehow. I've had a E4 1618 and tried a E4 1719 setting (1719 from optimal), it didn't POST. Then I changed it to BD 1719 (full three last bytes from optimal) and it worked. Counting from zero, the 6th byte is reg E4 (except the 7th bit). 7th ROMSIP CPU multi byte is reg E5 (with a mask). byte 7 bit 0 is reg E4 bit 7 (RD2WR delay). byte 7 bits 5:3 are reg E5 bits 6:4 Now I need to check ROMSIPs for valid byte combos. So byte 6 controls SYSDCOUT delay and SYSDCIN delay. Byte 7 controls W2R delay and WR data delay. Some ROMSIP bits seem unused by the registers, maybe they control some other regs maybe combined with byte 5. Edited June 24, 2021 by Antinomy 3 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 24, 2021 Author Crew Share Posted June 24, 2021 O.K. CPU multi part byte 2. Looks like byte 2 is always the same in ROMSIP and depends only on multi: After that, bytes 3 and 4 are 00. But there is one notable exception - DFI (and ECS) that use another writing, in fact, two of them. First is a usual ROMSIP entry, second is an entry modified by DFI, let's call it 3A 02 (by bytes 3-4). The third is another DFI entry, I'll call it CA 02. As you can see, in all cases byte 2 remains the same, only bit 7 is set to 1. In 3A 02 byte 1 bit 5 is set to 1, bytes 3 and 4 are 3A 02. In CA 02 byte 1 bits 5 and 3 are set to 1, bytes 3 and 4 are CA 02. Do not, that only these bits in byte 1 are modified. Other bits depend on byte 0 that are use for optimal/aggressive settings. Purpose of these bytes is unkown AFAIK but feel free to test DFIs modded settings. 3 Quote Link to comment Share on other sites More sharing options...
digitalbath Posted June 24, 2021 Share Posted June 24, 2021 (edited) 5 hours ago, Antinomy said: OK, the last three bytes of each multiplier in CPU part of ROMSIP are connected to b0d0f0 rE4-E7. Whice is S2K CONTROL 1 REGISTER. It configures timings of S2K (EV6) bus. But you can't change any bit in the ROMSIP, they are connected somehow. I've had a E4 1618 and tried a E4 1719 setting (1719 from optimal), it didn't POST. Then I changed it to BD 1719 (full three last bytes from optimal) and it worked. Counting from zero, the 6th byte is reg E4 (except the 7th bit). Nice find! No wonder E4 didn't work with 1719. As far as I tested, faster sips E4, ED needs lower values like 1618 or 1518. Slower sips like DB needs higher numbers like 1719 or 1821. You can change the last number from 1518 to 1519 and it will work. It's time to make some tests here. I hope I will find the time to do this. Edited June 24, 2021 by digitalbath 4 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 24, 2021 Author Crew Share Posted June 24, 2021 13 minutes ago, digitalbath said: As far as I tested, faster sips E4, ED needs lower values like 1618 or 1518. Slower sips like DB needs higher numbers like 1719 or 1821. You can change the last number from 1518 to 1519 and it will work. I've made a list from ROMSIPs you've sent - Trats, Shuttle, Taipan, Manta TX, LP_B_619, k12r4, DFI U400s-al, DFI_LP_B (all of them). Here are all the combos for last three bytes: Reds are what I think as typos, anomalies. Though, might help in the research. 2 Quote Link to comment Share on other sites More sharing options...
digitalbath Posted June 24, 2021 Share Posted June 24, 2021 @Antinomy thx. Byte 5 effect in speed and memory bandwidth. XB has a lower bandwidth (and latency?) then X4 and XD. DX is in general slower then EX. E4 and ED are equally fast. I am not sure where the difference is. I've combined for my first sips DB to a DD. They're still slow (~EB), but they got a better bandwidth. 2 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 25, 2021 Author Crew Share Posted June 25, 2021 (edited) O.K. looks like I've found the byte 2. This table sure looks familiar if you compare with byte 2 table from above. Still, a long read is ahead. I think I'll take a break. P.S. found a nice list of AMD datasheets, gotta make a local copy of that: https://en.wikichip.org/wiki/amd/List_of_AMD_publications Edited June 25, 2021 by Antinomy 3 Quote Link to comment Share on other sites More sharing options...
digitalbath Posted June 25, 2021 Share Posted June 25, 2021 (edited) I'll start here with BIOS modding instruction for beginners. I hope my text is understandable. I am open minded for improvements or error corrections. For the first part, I start here with AWARD BIOS disassembly / change romsips / assembly of BIOS modules. 1.0 assembly - disassambly BIOS modules and change romsips in AWARD BIOS I start modding AWARD BIOS with disassembling and assembling BIOS modules. This is essential to be able to edit the system BIOS module. This method can be used for every AWARD BIOS, not only for NF2 boards. I will explain this method in an example. I will mod here a MSI Delta2 6.0 BIOS. 1.1 Tools we need: awdbedit, hex editor, modbin6 and cbrom32_198. Modbin / cbrom needs a DOS System, so I use a XP System to mod my BIOSes. 1.2 I start with extracting all modules to a seperate folder (here: bin). I use awdbedit to do this: Be aware: Do not edit your BIOS in awdbedit! Now we got our BIOS modules extracted to a seperate folder. The System Module is simple to find (always 128KB) 1.3 disassemby BIOS file Now we need to unload all BIOS modules except the system module. I will use cbrom32 to do this. commands in cbrom: /d -list all modules /modulename release -delete module /modulname extract -extract module /isa modulname - add isa module /modulename filename – add module to BIOS file First, I open two DOS Command boxes. Then i list in the first box all modules from the unmodded BIOS. This will be my lookup table. I copy the unmodded file (here w6570nms.bin) and rename it to "empty_b6a.bin" (name does not matter here). This will be my "empty.bin" BIOS file. I will use the release command in the second box to delete all modules except System BIOS module (most module #0). cbrom32_198 empty_b6a.bin /logo release cbrom32_198 empty_b6a.bin /vga release cbrom32_198 empty_b6a.bin /pci release ---> B enter cbrom32_198 empty_b6a.bin /pci release cbrom32_198 empty_b6a.bin /group1 release cbrom32_198 empty_b6a.bin /group0 release cbrom32_198 empty_b6a.bin /ygroup release cbrom32_198 empty_b6a.bin /epa release cbrom32_198 empty_b6a.bin /acpi release cbrom32_198 empty_b6a.bin /xgroup release Then command cbrom32_198 empty_b6a.bin /d to list my empty.bin file. We see all modules are deleted, only system module is left. I duplicate my empty.bin file. I will need this later. Then I copy all extracted BIOS modules (from point 1.2) into folder. 1.4 edit System module I open the System module 6A61BM4K.BIN (128KB) with my hex editor. 1.4.1 Athlon XP-M name I search for "unknown CPU Type" and change this label to "AMD Athlon XP-M". Never change the size of the system module! 1.4.2 change romsips I search here for hex letters "65D0": All romsips tables begin with 65D0. One table has the size of 100h. This BIOS has 6 Tablles, so the romsips ends after 600h. I mark all tables (600h!) and paste the tables with the romsips I want (here 619XT). Now the system module is modded and I safe the file. 1.5 assembly BIOS file We now need to compress the modified system module. cbrom32_198 empty_b6a.bin /other 5000:0 6A61BM4K.bin (modded sytem module) This command compresses the modified system module into the BIOS file. This makes the BIOS file unusable, but this command duplicates also a copy to a file named "bios.rom". This is the file we need. I delete the unusable empty.bin file and replace it with my copy. I open the bios.rom file and the restored empty.bin copy. We mark and copy complete code in bios.rom (length=13911h!), switch to the restored empty.bin and jump to offset 10000h. This is where the system module beginns. We mark the length of the bios.rom (13911h) after the offset 10000h. Then paste the marked code with modded / compressed code. Fill with FF if the new code is shorter then the old code. Save and exit. cbrom32_198 empty_b6a.bin /d Everything looks fine. Now I will fill the BIOS wit the modules. This time, the order to fill the modules is important! cbrom32_198 empty_b6a.bin /xgroup awardext.rom cbrom32_198 empty_b6a.bin /acpi ACPITBL.BIN cbrom32_198 empty_b6a.bin /epa AwardBmp.bmp cbrom32_198 empty_b6a.bin /ygroup awardeyt.rom cbrom32_198 empty_b6a.bin /group0 _EN_CODE.BIN cbrom32_198 empty_b6a.bin /group1 BGROUP.BIN cbrom32_198 empty_b6a.bin /pci NV2PXES.NIC cbrom32_198 empty_b6a.bin /pci NVRAID.ROM cbrom32_198 empty_b6a.bin /vga CR17NZ.ROM cbrom32_198 empty_b6a.bin /logo Platinum.BMP cbrom32_198 empty_b6a.bin /d compare in case I made a mistake here: 1.6 conclusion: The modified BIOS files looks fine and is ready to use. CBROM did the checksum for us. This method to mod a BIOS file is not the fastest one, but necessary if you want to mod the strings (BIOS items) in the system module (more on this in another chapter). This method works with every BIOS (AN7 for example) 1.7 alternative There is a second and faster way to change romsips: open your BIOS file with modbin modbin creates a temporary ORIGINAL.BIN (128KB) file. This is the system module edit ORIGINAL.BIN, change romsips (1.4) and safe the modified ORIGINAL.BIN file. Safe as... in modbin and quit modbin. modbin will checksum for you end Edited June 25, 2021 by digitalbath 7 1 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 28, 2021 Author Crew Share Posted June 28, 2021 (edited) Another interesting attack vector is BIOS changelogs. Here is a compare between two DFI BIOSes and their changelog. Looks like the last line about bandwidth refers to changes in offset 5D0h - 1618 has been modified to 1518. Which according to previous data should be SYSDCIN delay (6 -> 5). CPU optimal is said to be more FSB friendly. We can see two things - zero byte (in CPU multi ROMSIP lines) is changed from 69 to 21, byte 5 is changed ED -> E4. Looks like 69 is more aggressive than 21. E4 and ED are known to be of same efficiency maybe it's fine tuning with minor changes. Another interesting thing are changes in chipset part of ROMSIP. Some changes are mapped by @digitalbath : Some are still to be figured out. DFI changelist might be handy: https://forums.overclockersclub.com/topic/115082-dfi-nf2-bioses/ Edited June 28, 2021 by Antinomy 3 3 Quote Link to comment Share on other sites More sharing options...
I.nfraR.ed Posted June 28, 2021 Share Posted June 28, 2021 (edited) Yes, I've seen the same, but better structured changelogs, here: https://www.lejabeach.com/DFI/BIOS/dfiultrabbios.html I've compared them in the past, but not so extensively. There's a mention about "improved" 3D Mark 2001SE performance, but I don't know if the changes are in the romsip tables or somewhere else. Maybe it's worth checking performance of the bioses "as-is" on a real Ultra B first, with same manual settings on diffrerent benchmarks, but that's a lot of work. 2004/01/31 2. Increase 3DMark2001 SE performance (compare to 12/31) AFAIK that 15 10 doesn't work and it had been changed in most (all?) modbioses. Apparently Oskar Wu changed it too. I believe what you've shown on the right side should be close to optimal for all boards with all multipliers (the multiplier tables part). NF3 and NF4 bioses also use "E4", although I don't know how relevant it is. Edited June 28, 2021 by I.nfraR.ed 3 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted June 28, 2021 Author Crew Share Posted June 28, 2021 (edited) 1 hour ago, I.nfraR.ed said: NF3 and NF4 bioses also use "E4", although I don't know how relevant it is. Might be more than relevant - "NVMM" http://www.rcollins.org/ Quote Solely designed and implemented NVIDIA memory module reference code (NVMM). n Revolutionary new design to work with any BIOS vendor, any CPU, North Bridge, South Bridge, and Super IO. n This design reduced code size, increased maintainability, and substantially reduced the support role of NVIDIA AEs for NVIDIA chipsets. 1 hour ago, I.nfraR.ed said: Maybe it's worth checking performance of the bioses "as-is" on a real Ultra B first, with same manual settings on diffrerent benchmarks, but that's a lot of work. Yes, I agree on this. Have two DFIs... Edited June 28, 2021 by Antinomy Quote Link to comment Share on other sites More sharing options...
digitalbath Posted June 28, 2021 Share Posted June 28, 2021 (edited) 9 hours ago, I.nfraR.ed said: I believe what you've shown on the right side should be close to optimal for all boards with all multipliers (the multiplier tables part). 100% agree 20 hours ago, Antinomy said: CPU optimal is said to be more FSB friendly. The Multi tables on the left side are mixed. They patched it more "cleaner". Zero Byte 21 is for me Interface optimal (at least 133MHz) and 69 is for aggressive. Nvidia used 21 also for their 200MHz / Interface aggressive sips. ------ Wu's previous work for Epox is also interesting: link Edited June 28, 2021 by digitalbath 1 Quote Link to comment Share on other sites More sharing options...
Tzk Posted June 30, 2021 Share Posted June 30, 2021 I'd like to add that there's actually two types of nvidia specific code for the ram controller inside the bios, depending on the board and (maybe?) chipset revision. We got NVDAMC and NVMM. NVDAMC is the memory controller firmware up to version 3.19. Nvidia then renamed it to NVMM and introduced version 4.x. Note that these versions are not compatible with each other. So if a board runs on 3.x (examples are Abit NF7, DFI Infinity/LP B, A7N8X), then you can't update to 4.x. Board won't boot. Some newer MSI boards (K7N2?) run on NVMM 4.35 and obviously won't boot on 3.19. I see no reason to use an older version than 3.19. It's the latest available NVDAMC version before NVMM got introduced and runs great in terms of stability and performance. Also note that the NVMM versions (ex: v4.62) extracted from Intel Nforce boards won't work on any socket 462 board. At least that was the conclusion when we tried it in the past. --- If you want to swap the BPL, you can do it with a regular hex editor as it isn't LZH compressed. Thus you don't need modbin to compress it and calculate the checksum. 3 Quote Link to comment Share on other sites More sharing options...
Tzk Posted June 30, 2021 Share Posted June 30, 2021 (edited) On 6/23/2021 at 4:19 AM, Antinomy said: options ROMs with performance tweaks (3D-fire for example - modified chipset registers?) Yes. You basically use the PCI registers of the chipset and set the desired settings via ISA or PCI option rom, right before the OS is loaded. There's two ways of doing this: a) you can just hardcode some settings b) you can write some data from modded bios settings to the CMOS register (bios settings are stored here) and load these cmos values from the option rom. This way you can add additional bios settings without hacking the whole bios. We did this on at least 3 or 4 boards (a7n8x-E, a7n8x v2.0, Abit, Epox?) and it works great. the cleanest solution would be to reverse engineer the bios and add those options in a native way. However i've already spend a bunch of hours looking into this on my A7N8X and even comparing different bios versions hasn't got me anywhere. Luckily Asus made 2 bios versions where each introduced a new bios setting, so the changes inside the code are clearly visible. However it looks like the hex strings which are used to define the bios items and the code which is controlled by them are stored right next to each other. So if there's an option added, then some offsets and pointers will break and the bios won't work anymore. My conclusion was that if we ever want to add completely new options into the bios which don't "recycle" unused bios items, then it's a ton of work. That's the point where i gave up... It's probably better to spend more time upon improving and understanding the romsips first. Edited June 30, 2021 by Tzk 3 Quote Link to comment Share on other sites More sharing options...
digitalbath Posted June 30, 2021 Share Posted June 30, 2021 (edited) 24 minutes ago, Tzk said: Some newer MSI boards (K7N2?) run on NVMM 4.35 and obviously won't boot on 3.19. little correction here. I did boot sometimes. The problem is, that the auto dimm timings aren't set correctly by the BIOS (f.e. tRAS value for tRCD, something like 2,5-7-3-4). After I set the timings to manuall mode, it did boot without problem. That was at least on my Delta2 board. Other boards could react different. Nevertheless I would not recommend to change a 4.xx version to 3.19. Some boards with 4.xx BPL seems not to work with other 4.xx version (shuttle SN45G). My newest BPL versions are NVMM 4.85 for AMI BIOS and NVMM 4.62 for AWARD. Edited June 30, 2021 by digitalbath 1 Quote Link to comment Share on other sites More sharing options...
Tzk Posted June 30, 2021 Share Posted June 30, 2021 (edited) On 6/23/2021 at 4:41 AM, Antinomy said: So these do look like CPU settings. I believe some of them are delays that are programmed during SIP packet. Might be lame, but I didn't see this info before. When i started looking into romsip modding i found this post by TicTac on pcper forums. See attached screenshot for content. So yes, these are indeed multi specific settings... This made me test my FSB stability at multi 7 or 7.5. If it is stable on these multis, then it'll run on any multi. However he didn't state what these settings are actually controlling. If we can find this out (also for the upper half of the romsips), then we might be able to push the fsb further. We also hit a hard FSB wall at about 263MHz right now, on the german Hardwareluxx Forums we got about 4 or 5 boards which won't pass 32M above 263Mhz, no matter what you do. Vdd, Vcore, Multi doesn't matter, some boards do even freeze when trying to set 264/265 MHz. No clue what causes this, might be some peripheral controller or even the chipset itself acting up. broken link: https://pcper.com/forums/?346001-ROMSIP-Table-Mod-Guide#post3100010 Edited June 30, 2021 by Tzk 3 Quote Link to comment Share on other sites More sharing options...
Tzk Posted July 2, 2021 Share Posted July 2, 2021 (edited) @Antinomy and @I.nfraR.ed shared their thoughts about superlocked cpus and cpu registers (MSR). Maybe we can identify superlocked cpus like this... They also mentioned a tool called Barton CRC (BCRC.exe). So i grabbed a few cpus and here's the result so far. Example screenshot of BCRC output: Here's the result which BCRC reported. The first columns is what i read from the cpu sticker (orange), latter ones are output of BCRC (blue). My conclusion so far is that the minor rev is rather random and the superlock plus the Crystal marker seems to be a more or less random guess. Nr Cpu Rating Stepping week Stepping ED Value CPUID Processor Code Major Minor Type Crystal Marker 11 Athlon XP 2600 AQZFA 0349 TPMW 2306h 06A0h Barton 0 2 locked AQYFA 12 Athlon XP 2600 AQXDA 0318 MPMW 2319h 06A0h Barton 0 15 unlocked unknown 13 Athlon XP 2600 AQXEA 0404 TPMW 2316h 06A0h Barton 0 12 unlocked unknown 15 Athlon XP 2600 AQYHA 0401 UPMW 2315h 06A0h Thorton w/512K 0 11 locked AQYFA 16 Athlon XP 2600 AQXEA 0403 WPMW 2316h 06A0h Barton 0 12 unlocked unknown 17 Athlon XP 2800 AQYHA 0409 SPMW 2315h 06A0h Thorton w/512K 0 11 locked AQYFA Edited July 5, 2021 by Tzk 5 Quote Link to comment Share on other sites More sharing options...
I.nfraR.ed Posted July 2, 2021 Share Posted July 2, 2021 (edited) These "possible crystal marker" and "possible parent crystal" are just educated guesses based on other parameters. The multiplier type is also probably guessed based on some parameters (major.minor rev, but maybe something else too). That minor revision is kind of strange, I would have guessed higher minor revision would mean a newer cpu, but based on your table - that is not the case. I've added a message box to the tweaker on app open that displays the info I currently have implemented. There's not much info about the topic, but K8 KBDG (BIOS and Kernel Developer's Guide for AMD AthlonTM 64 and AMD OpteronTM Processors) has the MSR register in question documented There's one more value, which is "Reticle Site" and I've included it in the info. Curious to see what different cpus show. Btw, reading and writing MSRs is quite easy. You can use the MSR Editor and MSR Walker in CrystalCPUID tool. PS: I'm thinking of writing a small tool that automatically dumps CPUID registers, MSRs and all the info like cpuid, name, family, model, revision, etc. This way, the comparisons would be easier and faster. Edit: Replaced the app with new build. I was reading wrong part of the register, but it should be ok now. nForce2XT_Debug_20210703.zip Edited July 2, 2021 by I.nfraR.ed 4 Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted July 3, 2021 Author Crew Share Posted July 3, 2021 (edited) CPU model Stepping Week Stepping Locked/unlocked Processor code Major Minor Type EdValue Crystal marker Athlon XP 2500+ AQXEA 0330 WPMW Unlocked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2500+ AQZFA 0411 SPMW Locked Barton 0 2 Locked 2306h AQYFA Athlon XP 2500+ AQXEA 0327 SPGW Unlocked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2500+ AQZFA 0350 SPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2500+ AQZFA 0347 VPMW Locked Barton 0 2 Locked 2306h AQYFA Athlon XP 2600+ AQYFA 0410 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ AQYFA 0410 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ AQXEA 0407 UPMW Locked Barton 0 12 Unlocked 2316h Unknown Athlon XP 2600+ AQZFA 0405 VPBW Locked Barton 0 2 Locked 2306h AQYFA Athlon MP 2800+ AQYHA 0416 UPAW Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon MP 2800+ AQYHA 0416 UPAW Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 3000+ AQYHA 0437 CPJW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP 2600+ SFF AQYHA 0351 MPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Athlon XP-M 2500+ AQXFA 0337 XPMW Unlocked Barton 0 2 Locked 2306h AQYFA Athlon XP-M 2500+ AQYFA 0342 MPM Unlocked Thorton w/512K 0 11 Locked 2315h AQYFA Sempron 3000+ ADYHA 0512 MPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Sempron 3000+ IQYHA 0444 VPMW Locked Thorton w/512K 0 11 Locked 2315h AQYFA Edited July 3, 2021 by Antinomy 1 Quote Link to comment Share on other sites More sharing options...
Tzk Posted July 4, 2021 Share Posted July 4, 2021 On 7/2/2021 at 3:12 PM, I.nfraR.ed said: There's one more value, which is "Reticle Site" and I've included it in the info. Curious to see what different cpus show. Perfect. So now we can use BCRC and your tweaker to read the values. Will retest the above mentioned cpus. @Antinomy A question regarding the forums and its editor: Is there a possibility to install a plugin for the WYSIWYG editor to include tables? The table above was just copy&paste from excel, but i can't change the table width... Not sure how you did it in your post. Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted July 4, 2021 Author Crew Share Posted July 4, 2021 10 hours ago, Tzk said: @Antinomy A question regarding the forums and its editor: Is there a possibility to install a plugin for the WYSIWYG editor to include tables? The table above was just copy&paste from excel, but i can't change the table width... Not sure how you did it in your post. Reticle site was 1 for all my CPUs. I've made copy and paste from Google docs, width pasted a bit more narrow than in my table, had to make it a bit more wide. 1 Quote Link to comment Share on other sites More sharing options...
Tzk Posted July 5, 2021 Share Posted July 5, 2021 (edited) On 7/2/2021 at 3:12 PM, I.nfraR.ed said: I've added a message box to the tweaker on app open that displays the info I currently have implemented. Just a thought: Wouldn't it be better if we could open that info box with a button inside the tweaker? So we don't have to close it on every tweaker launch if we want to "just" change timings. Also the frequency and FSB display is currently broken on A7N8X, right? Tweaker reports 151Mhz and Multi 11 while Cpu-Z shows the actual values (133 + 12.5x). Besides that the MSR values between BCRC and Tweaker match, well done! Edited July 5, 2021 by Tzk Quote Link to comment Share on other sites More sharing options...
Crew Antinomy Posted July 5, 2021 Author Crew Share Posted July 5, 2021 (edited) 37 minutes ago, Tzk said: Wouldn't it be better if we could open that info box with a button inside the tweaker? This is just a test build. We don't even know, if we need this info in the future. For timings you can use the regular version. Edited July 5, 2021 by Antinomy 1 Quote Link to comment Share on other sites More sharing options...
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