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Posted
On 7/28/2020 at 8:54 AM, yosarianilives said:

lpddr3, Imho it's as much Ddr3 as fbdimm is ddr2 or gddr4/5 is ddr4.

Nope.

On 7/28/2020 at 8:54 AM, yosarianilives said:

The data widths, etc are completely different from Ddr3 memory among a number of other differences.

Not exactly. LPDDR3 standard permits use of different data widths but in case of general notebooks it's not quite so. Generally speaking DDR3L or LPDDR3 SO-DIMM module is simply one that can work at 1.35V. Usual DDR3 SO-DIMMs work at 1.5V. So generally speaking any DDR3L module will work in DDR3 environment and vice versa, a DDR3 SO-DIMM that works stable at 1.35V will work in DDR3L system.
Thus speaking, I don't think it's necessary to make a separate category for them especially since CPU-Z doesn't tell them from regular ones.
I'm open for arguments and opinions though.

Posted
8 hours ago, Antinomy said:

Not exactly. LPDDR3 standard permits use of different data widths but in case of general notebooks it's not quite so. Generally speaking DDR3L or LPDDR3 SO-DIMM module is simply one that can work at 1.35V. Usual DDR3 SO-DIMMs work at 1.5V. So generally speaking any DDR3L module will work in DDR3 environment and vice versa, a DDR3 SO-DIMM that works stable at 1.35V will work in DDR3L system.
Thus speaking, I don't think it's necessary to make a separate category for them especially since CPU-Z doesn't tell them from regular ones.
I'm open for arguments and opinions though.

DDR3L isn't relevant here, that's just DDR3 at a different voltage.  LPDDR3 is different.  I cannot stress enough that DDR3L and LPDDR3 are not interchangeable terms!

Fundamentally LPDDR3 is not a Low Power version of DDR3.  Rather, it is the third version of LPDDR memory, like how we have GDDR memory.  This applies to other generations as well, from LPDDR1 to LPDDR5.

The biggest difference I'd point to when it comes to LPDDR3 specifically is that the command/address bus is double data rate, as well as the data bus.  Regular DDR isn't getting a double data rate cad bus until DDR5.  However there are a number of other details, as this excellent article covers; https://blogs.synopsys.com/committedtomemory/2014/01/10/when-is-lpddr3-not-lpddr3-when-its-ddr3l/.  What yos means about data widths is an LPDDR chip can be 32, 64 or even 128 bits wide whereas a normal DDR device is 4, 8 or 16 bits.  The cad bus width changes too.  Related to this is the fact that LPDDR never appears on SODIMMs, it is always soldered (or stacked in the case of Intel Lakefield's LPDDR4X).

As technology moves on we're seeing greater and greater divergence between LPDDR and DDR.  We see for example that the Intel i7-10710U supports LPDDR3-2133 and not DDR3, and also supports LPDDR4-2933 but DDR4 only up to 2666, despite a DDR4-2933 standard being available.  An older CPU like the i7-8665U supports DDR4 and not LPDDR4, but does support LPDDR3 (and not DDR3).  We also now have LPDDR4X standards up to 4266 while DDR4 is stuck at 3200.

Because of this I'd come down strongly on the side of saying LPDDRx should be distinguished from DDRx.  Maybe LPDDR1 and DDR1 could stay together as their differences come down to more economical self-refresh operation, though I'm not sure LPDDR1 (or 2) are used in anything but phones anyway.  LPDDR3, LPDDR4, and LPDDR5 should definitely be separate though, IMO.  LPDDR4X is fundamentally the same as LPDDR4 so could be in the same category, although as a database it might be good to distinguish them (this would also prevent stock LPDDR4X frequency subs getting too many points because of being so far ahead of LPDDR4).

CPU-Z not being able to tell the difference is a problem, and it's something the CPUID guys ought to look at.  It's not the first time there's a problem with CPU-Z, it still calls the Athlon 3000G 12nm Picasso, it's 14nm and a 2-core die.

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Posted

Well if it's the intention to have another ranking for memory records, a missing way to detect LPPDR is probably the show stopper. On the other hand, this could be also added, just to be more exact. We know that some SoCs use LPDDR. But currently, they stand with regular DDR memory in our db. We would be able to offer more correct information for those. But as we are more a overclocking database than a technical database, it wouldn't be much of a benefit I guess.

But if it's possible to detect this properly, I don't see why we shouldn't do this. Even though I don't expect much of it -overclocking wise. (But honestly don't know much about those stuff, so I actually cant judge.) Has anyone already asked CPU-Z devs about this? Maybe we should postpone discussion till we have an answer here. I guess they would first need to find a way to properly detect this + making lot of testing.

42 minutes ago, mickulty said:

CPU-Z not being able to tell the difference is a problem, and it's something the CPUID guys ought to look at.  It's not the first time there's a problem with CPU-Z, it still calls the Athlon 3000G 12nm Picasso, it's 14nm and a 2-core die.

Well the issue seems to be, that regular Picasso and the 3000G share exact the same CPUID. This ID is should be Picasso only and as we all know the difference to Raven Ridge is the Die shrink to 12nm + some minor modification. The core of the 3000G was already identified as Dali and AMD itself states 14nm for this CPU. But for some reason AMD _wants_ to let all people believe it is pure Picasso which it simply can't be. 

Anyway the identical ID is the problem why CPU-Z detects it wrong. I contacted CPU-Z author about the problem and hope for an answer.

AFAIU from this file in AMD Linux driver, the Dali IGP shares also the same Device ID like Picasso, 15D8. But they doing some code dance to separate Raven2, Pollock and Dali from pure Picasso party, mainly by reading Asic revision. Unfortunately this seems to be not the same Revision which GPU-Z shows us.

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Posted
14 hours ago, mickulty said:

a problem with CPU-Z, it still calls the Athlon 3000G 12nm Picasso, it's 14nm and a 2-core die.

A CPU-Z txt report file would be useful on this one.

Thank you for clarification, I indeed messed up LPDDR3 with DDR3L. Again, we need txt reports from such systems to help with reporting this bug to CPU-Z author. I could contact Franck on this one.

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