chew*

Infrareds No cmos battery tweak. Massmans not genuine windows activation pop up tweak

Apples to apples 12-12-12 2933 is less than 3 seconds ahead of 16-14-14 2933. Timings are worth something...but not a whole lot. Cas latency is worth the most.

Ok Here goes timings versus fabric single rank and dual rank. Single rank 2933 Single rank 3200 Dual Rank 2666 Dual rank 2933 Conclusion Single rank speed + fabric wins ( we pretty much knew this ) Dual rank Application specific tossup. cheers

Ahh well that explains why it did not work.

Except for the fact. He already ran smt off tests and still had said issue. Least thats what he said.

All ref clock boards are using an ASMEDIA chip. I could be wrong but this was for fine grain control. The cpu is actually capable without the chip. 1.2v was deemed safe in reviewers guide yes. Why anyone would just jack voltages up without verifying that they are actually helping anything is beyond me however. First thing I did was lower all voltages looking for potential overlooked gains. Then I retested raising.

Be advised bclk is strapped to PCI. Many devices will not like high PCI, some will corrupt some will break. Including onboard devices hard drives vga....... Best to disable all when "benching at high PCI" SOC may help stabilize IMC with 4 dims, no clue ( don't have 4 dims ) but with 2x8g single sided Samsung B die 1.0 is fine.

The latest microcode that I have hates odd CL. try running even CL. I would physically look at your sticks to confirm single sided. 2T is what my Hynix was defaulting at on my double sided sticks. Double sided is almost the equivalent of running 4 single sided which also default at 2T. Not sure why everyone is obsessed with running SOC @ 1.2 I run all my chips at 1.0 just fine. less volts in less heat output.

I changed my password to avoid temptation for the league.....so appearance only changes baseline and for some bug reporting. win 10 HPET enabled win 7 hpet enabled

Ok thx i'm not crazy. UD5 performance in 7 is garbage...

flanker test wprime for me. I'm seeing preety large variance between win7 and 10 not sure why. just 32m needed for now.

Thx i got someone on this. Its above my pay rate now.

I'm running high LLC and 1.00 SOC my board defaults at 1.1. I found in my case chasing highest clocks I can drop it .100 to drop heat. For 4 dims populated yes that would be a tad to low by default imo. My biggest concern is not your board but the report of the crosshair also exhibiting this issue. I'm under the understanding that they are working on updating mainstream boards second top tier first......but if ch6 has this issue..it should have latest agesa already.

OK the SOC voltage is preety damn low. It should be around 1.00 minimum and the range is 1.0-1.20 bump to gain stability. The bottom voltage Dram termination voltage should be equal to 50%

The reason I wanted you to test win 7 is..... Logical Processor to Cache Map: *--------------- Data Cache 0, Level 1, 32 KB, Assoc 8, LineSize 64 *--------------- Instruction Cache 0, Level 1, 64 KB, Assoc 4, LineSize 64 *--------------- Unified Cache 0, Level 2, 512 KB, Assoc 8, LineSize 64 *--------------- Unified Cache 1, Level 3, 16 MB, Assoc 16, LineSize 64 -*-------------- Data Cache 1, Level 1, 32 KB, Assoc 8, LineSize 64 -*-------------- Instruction Cache 1, Level 1, 64 KB, Assoc 4, LineSize 64 -*-------------- Unified Cache 2, Level 2, 512 KB, Assoc 8, LineSize 64 -*-------------- Unified Cache 3, Level 3, 16 MB, Assoc 16, LineSize 64 --*------------- Data Cache 2, Level 1, 32 KB, Assoc 8, LineSize 64 --*------------- Instruction Cache 2, Level 1, 64 KB, Assoc 4, LineSize 64 --*------------- Unified Cache 4, Level 2, 512 KB, Assoc 8, LineSize 64 --*------------- Unified Cache 5, Level 3, 16 MB, Assoc 16, LineSize 64 ---*------------ Data Cache 3, Level 1, 32 KB, Assoc 8, LineSize 64 ---*------------ Instruction Cache 3, Level 1, 64 KB, Assoc 4, LineSize 64 ---*------------ Unified Cache 6, Level 2, 512 KB, Assoc 8, LineSize 64 ---*------------ Unified Cache 7, Level 3, 16 MB, Assoc 16, LineSize 64 ----*----------- Data Cache 4, Level 1, 32 KB, Assoc 8, LineSize 64 ----*----------- Instruction Cache 4, Level 1, 64 KB, Assoc 4, LineSize 64 ----*----------- Unified Cache 8, Level 2, 512 KB, Assoc 8, LineSize 64 ----*----------- Unified Cache 9, Level 3, 16 MB, Assoc 16, LineSize 64 -----*---------- Data Cache 5, Level 1, 32 KB, Assoc 8, LineSize 64 -----*---------- Instruction Cache 5, Level 1, 64 KB, Assoc 4, LineSize 64 -----*---------- Unified Cache 10, Level 2, 512 KB, Assoc 8, LineSize 64 -----*---------- Unified Cache 11, Level 3, 16 MB, Assoc 16, LineSize 64 ------*--------- Data Cache 6, Level 1, 32 KB, Assoc 8, LineSize 64 ------*--------- Instruction Cache 6, Level 1, 64 KB, Assoc 4, LineSize 64 ------*--------- Unified Cache 12, Level 2, 512 KB, Assoc 8, LineSize 64 ------*--------- Unified Cache 13, Level 3, 16 MB, Assoc 16, LineSize 64 -------*-------- Data Cache 7, Level 1, 32 KB, Assoc 8, LineSize 64 -------*-------- Instruction Cache 7, Level 1, 64 KB, Assoc 4, LineSize 64 -------*-------- Unified Cache 14, Level 2, 512 KB, Assoc 8, LineSize 64 -------*-------- Unified Cache 15, Level 3, 16 MB, Assoc 16, LineSize 64 --------*------- Data Cache 8, Level 1, 32 KB, Assoc 8, LineSize 64 --------*------- Instruction Cache 8, Level 1, 64 KB, Assoc 4, LineSize 64 --------*------- Unified Cache 16, Level 2, 512 KB, Assoc 8, LineSize 64 --------*------- Unified Cache 17, Level 3, 16 MB, Assoc 16, LineSize 64 ---------*------ Data Cache 9, Level 1, 32 KB, Assoc 8, LineSize 64 ---------*------ Instruction Cache 9, Level 1, 64 KB, Assoc 4, LineSize 64 ---------*------ Unified Cache 18, Level 2, 512 KB, Assoc 8, LineSize 64 ---------*------ Unified Cache 19, Level 3, 16 MB, Assoc 16, LineSize 64 ----------*----- Data Cache 10, Level 1, 32 KB, Assoc 8, LineSize 64 ----------*----- Instruction Cache 10, Level 1, 64 KB, Assoc 4, LineSize 64 ----------*----- Unified Cache 20, Level 2, 512 KB, Assoc 8, LineSize 64 ----------*----- Unified Cache 21, Level 3, 16 MB, Assoc 16, LineSize 64 -----------*---- Data Cache 11, Level 1, 32 KB, Assoc 8, LineSize 64 -----------*---- Instruction Cache 11, Level 1, 64 KB, Assoc 4, LineSize 64 -----------*---- Unified Cache 22, Level 2, 512 KB, Assoc 8, LineSize 64 -----------*---- Unified Cache 23, Level 3, 16 MB, Assoc 16, LineSize 64 ------------*--- Data Cache 12, Level 1, 32 KB, Assoc 8, LineSize 64 ------------*--- Instruction Cache 12, Level 1, 64 KB, Assoc 4, LineSize 64 ------------*--- Unified Cache 24, Level 2, 512 KB, Assoc 8, LineSize 64 ------------*--- Unified Cache 25, Level 3, 16 MB, Assoc 16, LineSize 64 -------------*-- Data Cache 13, Level 1, 32 KB, Assoc 8, LineSize 64 -------------*-- Instruction Cache 13, Level 1, 64 KB, Assoc 4, LineSize 64 -------------*-- Unified Cache 26, Level 2, 512 KB, Assoc 8, LineSize 64 -------------*-- Unified Cache 27, Level 3, 16 MB, Assoc 16, LineSize 64 --------------*- Data Cache 14, Level 1, 32 KB, Assoc 8, LineSize 64 --------------*- Instruction Cache 14, Level 1, 64 KB, Assoc 4, LineSize 64 --------------*- Unified Cache 28, Level 2, 512 KB, Assoc 8, LineSize 64 --------------*- Unified Cache 29, Level 3, 16 MB, Assoc 16, LineSize 64 ---------------* Data Cache 15, Level 1, 32 KB, Assoc 8, LineSize 64 ---------------* Instruction Cache 15, Level 1, 64 KB, Assoc 4, LineSize 64 ---------------* Unified Cache 30, Level 2, 512 KB, Assoc 8, LineSize 64 ---------------* Unified Cache 31, Level 3, 16 MB, Assoc 16, LineSize 64 each zen thread is being registered as an individual core with its own L2 and L3 cache I have a weird feeling that this and some other gremlins some are experiencing could be related......

can you take a picture of the bios voltages for me, namely dram dram termination and SOC

pull 3 sticks and run

Mystical can this program run in win 7? If so can you please try it for me? flanker I have an idea that its not related to that stuff nor smt. errata I doubt misinformed as to how much cache really exists possibly or the memory. Before you go rip a windows install put in one quick test. Use 1 stick please run and tell me if they are double sided and if it runs. Also what is the default SOC voltage on that board.

You sir are on a cascade and in memory coldbug temp range Run @2400-2666 or use ln2 lol.

LOL 3.9 bad 4.1 good. you want to spend $329.00 USD at min to bin for a water/air chip to gain 100-200? $500 chip binning for ln2 will get expensive quick.

I think he knows lol. I referenced massman as the source. Credit where credit is due as always like he has done for me.

Clearly the RX 480 8gb or not stands no chance vs the 6900k in 32m pi

K will do when im back home. Road trip till tomorrow.

Got any messenger services anymore? Or to busy to chat with an old timer.

Its what AMD needed for sales. In realworld ive only been able to keep a system on ln2 for 12 hours straight gaming lol. Not 24/7 . Fairly certain vcore is right.