January 21, 201510 yr It's a Venice core. CPUz error. Most likely, I asked Mihai to take a pic of the IHS so we can check the SSPEC.
January 21, 201510 yr Awesome score! Regarding SSE2 and SSE3 as a minimum requirement for OpenCL: SSE3 is important because otherwise there isn't really a performance advantage running it in parallel. But the driver itself decides, what is 100% necessary to run the implementation. I didn't know it before, but the AMD drivers are fine with SSE2. Intel on the other hand needs SSE4.1 to make it work.
January 21, 201510 yr Awesome score! Regarding SSE2 and SSE3 as a minimum requirement for OpenCL: SSE3 is important because otherwise there isn't really a performance advantage running it in parallel. But the driver itself decides, what is 100% necessary to run the implementation. I didn't know it before, but the AMD drivers are fine with SSE2. Intel on the other hand needs SSE4.1 to make it work. Interesting as to why that might be..... So AMD 64 FTW in this competition now
January 21, 201510 yr It's a Venice core. CPUz error. If it was a Venice core , shouldnt there be an indication in cpu-z , about SSE3 capability ? It's a Clawhammer 512KB L2 (ADA3400AEP4AR) http://www.cpu-world.com/CPUs/K8/AMD-Athlon%2064%203400+%20-%20ADA3400AEP4AR.html
January 21, 201510 yr But ... What is really interesting about this submission , is the age of this particular cpu. I dont know how the system calculated 11years and 2 months. ADA3400AEP4AR Core stepping CG Stepping code CAA2C That cpu is late 2004 - early 2005
January 21, 201510 yr Author If it was a Venice core , shouldnt there be an indication in cpu-z , about SSE3 capability ? It's a Clawhammer 512KB L2 (ADA3400AEP4AR) http://www.cpu-world.com/CPUs/K8/AMD-Athlon%2064%203400+%20-%20ADA3400AEP4AR.html Not if it's being misread. Nothing can be taken for granted. @ Mat - You're killing me. I've asked this before, is SSE2 supported or just SSE3? It's kinda important because it changes the platform that we should be benching on. Time is short, we kinda need to know this. Intel on the other hand needs SSE4.1 to make it work. This is not a true statement. MacsBeach's P4 560 does not have SSE4.1. Edited January 21, 201510 yr by Mr.Scott
January 21, 201510 yr Author But ... What is really interesting about this submission , is the age of this particular cpu. I dont know how the system calculated 11years and 2 months. ADA3400AEP4AR Core stepping CG Stepping code CAA2C That cpu is late 2004 - early 2005 September of 2003 EDIT- Saw the CPU pic. Bench works on SSE2. This changes everything. Edited January 22, 201510 yr by Mr.Scott
January 22, 201510 yr September of 2003 I disagree ADA3400AEP4AR was produced only in Stepping code CAA2C. Stepping code CAA2C on CG core , was manufactured on the last quarter of 2004 , that's why the majority of cpu's based on CAA2C have a production date of 10th to 30th week of 2005.
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