A7N8X-E Deluxe as an alternative for socket 462

[TerraRaptor]

12 minutes ago, Thorn said:

Legit? ?

Highly likely. In Russian internet there was bios modder FatumNNM who claimed to build custom bios for 8rda that was stable over 280mhz with hynix ram. 

[Thorn]

Really sick values then. Would be nice to get hold of the bios, maybe someone talented can find the magic inside. BH5 also makes me thinking. Thought 3.2V+ was the minimum (good ones) to reach 250-MHz+ stable.

[digitalbath]

On 2/3/2020 at 9:45 PM, TerraRaptor said:

Highly likely. In Russian internet there was bios modder FatumNNM who claimed to build custom bios for 8rda that was stable over 280mhz with hynix ram. 

I found his posts in a russian thread (via google translator). He wrote, he got max fsb 283MHz with his Forsage mod BIOS. I found his BIOS here:

http://bierbude.spdns.org:2302/Mod-BIOS und mehr/Epox/8RDA+/
 

this is the changelog:

Bios: Forsage based on 8RDA4729 01/25/2006

Attention: I don’t bear any responsibility for the work of this BIOS !!!

List of changes / additions:

1 . CPU Interface Table 133, 166 & 200 MHz FSB: (ROMSIP Modding by FatumNNM):
- CPU Interface -> Optimal: max. fsb = 283 MHz (in the 2nd channel on Hynix DT-43).
- CPU Interface -> Aggressive: Increased 3D stability & efficiency at c. > 10 and> 10.5
(max. fsb = 283 MHz (in 2 channel on Hynix DT-43).


2. BPL updated to version 3.09
3. Command Per Clock: 1T
4. CPU Disconnect feature patched according to nVidia Tech recommendations
5. Dimm Driving Stregth: 6
6. Slew Rate: 7
7. Alpha Memory Timing: 1-3-3-3-3-3-4
8. Increased stability of 3DMark2001SE & 3D applications at higher FSB frequencies
9. Soft L12-mod for non-modal Tbred, Semptron & Barton
10. All modules responsible for operating at higher FSB frequencies were rewritten by me from scratch.
In past bios (Sprinter 0.1), I used the 3D-Fire module (by Hell-Fire),
it has now been replaced by my NF2Ultra (by fatumNNM).


PS: Since mobile versions of AMD are not widespread in our country, I did not begin to correctly detect them.
If this is useful to someone, then let me know and I will add this support.

looking at the romsips:

They seems to be based on DFI-12-31 / Taipan0.3 ED. But he also wrote about more improvements...

Edited February 5, 2020 by digitalbath

[I.nfraR.ed]

Judging from the discussion in the rom.by forum, he tweaked the alpha-timings for specific Hynix chips.

https://www.rom.by/forum/Moddenye_biosy_dlja_nForce_2?page=3

perhaps something to do with the module next to the BPL, like I reported here: 

or the BPL itself. You might find something useful by comparing the bioses.

I don't have time for this now, but will get back to it some time in the future.

There are many parts of the bios that are still unclear to me.

I can read and understand Russian most of the time, so if you need something translated (which google translate messed up), I could probably help.

Overall they don't seem to have a positive feedback on this Forsage bios.

 

PS: He says that he fixed the timings for the specific RAM IC by reading its datasheet and changing them in the bios (probably in the block I've talked about).

 

PS2: He also talks about a program he wrote BIOS Explorer for nForce2-bioses (BEXplo.7z) which can mod ROMSIP and CPC, but it's for 2Mbit bioses only and can't find a working link.

Edited February 5, 2020 by I.nfraR.ed

[digitalbath]

I compared the FatumNNM Fosage BIOS with the official EPOX BIOS 4729. The BPLs (3.09) are the same. The blocks after the BPL (starting with the fail-safe Romsips) are identical in most cases. The differences are in the end of the first part. It seems this block belongs to the decompression module.

There are also changes in the system BIOS. Most strings have been changed. I don't know yet what exactly was changed. i need more time to figure it out...

 

FatumNNM wrote, he used a tool named BIOS patcher. I downloaded it from rom.by and uploaded it here:

http://bierbude.spdns.org:2302/USER UPLOADS/digitalbath/BP_ROM.by/

Here are the options, what this tool does:

Rom.by contains more Information on BIOS modding. it's worth a look inside.

http://www.rom.by/biosedit.htm

I didn't find the Explorer program either

 

Edited February 8, 2020 by digitalbath

[TerraRaptor]

Atthached is archive with his achivements, thanks to Antinomy who shared it with me last year. May be of interest for you. No description what these bioses are from me. "Bios explorer" is also there.

8RDA_series.zip

[I.nfraR.ed]

I've tried the patcher before and have it in my archive, but I don't think it does anything interesting for our modded and newer bioses.

 

[digitalbath]

I also don't think it will help us. The program adds detection for mobile processors and FID detection for the K7 processors.
The interesting part is that the patch adds two more modules with the patch.

[digitalbath]

I hope someone can confirm that:

edit: i think it will help us to test the romsips

Edited February 12, 2020 by digitalbath

[I.nfraR.ed]

Yes, I've tested half of these, but can't confirm them all, since I stopped testing.

14h, 23h and 27h seem in line with what I've found (just from memory, I might be wrong).

I have changed most of them in wpcredit and the one with most impact was the 14h, but others need thorough testing as well.

[digitalbath]

69h and 6Fh seem to have the most impact on the performance going from 88h + 88h down to 22h + 22h.
I will have to test more, but it will take longer...

[I.nfraR.ed]

A new tweaker coming into town ?

 

Primary and secondary (alpha) timings read done. Will implement apply action soon.

Every control reports if the value has changed and the Apply button would only set changed values.Those values are marked with yellow background.

If the app reads a value (still in the defined range) that doesn't match any value in the dropdown, it will be automatically inserted in the list as a new option. For example - the default TREF on my board at 200MHz FSB seems to be 1562, while I only have a predefined 1560 in the dropdown list.

 

Here's what I've planned

DRAM

• primary and secondary timings
• drive strengths and slew rate per DIMM
• data scavenged rate, autoprecharge, superbypass, sync mode memory bypass

Chipset

• AGP and PCI latencies, Side Band Addressing, CPU Disconnect, AGP Fastwrite
• Tweakable ROMSIP registers

Profiles

• Predefined chipset profiles for different RAM ICs (same as @digitalbath's approach)
• Maybe some predefined profiles for DRAM timings as well
• Save/Load custom profiles

Good to have

• SMBus control of the integrated nForce2 PLL - don't have experience there

The Bad

• It will need .NET 2.0 framework and would have a little higher memory footprint than e.g. NF2Tweaker.

Hit me with other ideas.

 

Edited April 10, 2020 by I.nfraR.ed

[Tzk]

That one looks great! What about an option to load and apply the values during windows boot? I love how everyone is still pushing socket a as hard as possible. Thanks for investing your time to create a new tweaker

Regarding the romsips: @digitalbath even went further and integrated these in shuttle, nf7 and asus bios. It‘ s all uploaded to the bierbude server, including the option rom sourcecode. Maybe you can take some settings from there? Heres what he did (sorry, german forums), the picture should speak for itself:

https://www.hardwareluxx.de/community/threads/amd-sockel-a-thread.584473/page-63#post-27414975

Might also be of interest for @TerraRaptor as these bios seem to run extremely well on asus.

bierbude.spdns.org:2302/USER%20UPLOADS/digitalbath/

Sadly i haven’t  had time to port his a7n8x-e changes to the non -e dlx yet. He even manged to get 2x1gb running at ddr500 on nf2 ? 

 

Edited April 11, 2020 by Tzk

[digitalbath]

A fantastic job Infrared!

The romsips profiles and tweakable romsips register will definitely help us!
If you need romsips profiles, you can find my profiles in my latest version of the ISA option rom (A6)

Beware! The older version of ISA-option-rom (A4) may have a bug on some boards. I will update all my BIOS versions to the latest version.

My Romsips profiles are not yet 100% final. We can definitely improve it, but I've had a good experience with it.

A7N8X-E_orom_A6.zip

[I.nfraR.ed]

Yes, I follow that thread on your forums  We (me and @TerraRaptor) were commenting your progress behind the scenes .

I've even tried your modded NF7 bios and it works, but didn't see a difference in maximum stable clocks with my setup.

Currently working on "documenting" all known registers. Take a look if you want and report back if you see some errors.

https://docs.google.com/spreadsheets/d/1ZDST3XGq0oE7YtQxAME29RtopA8QcePCaHa2NBRHaB8/edit?usp=sharing

PS: Second table, reg 94, bits [2:0] could possibly be another timing, however it might be a reserved value.

AFAIK I've tried it before and it didn't accept the changed value.

 

 

Also uploaded the nf7 files to my github: https://github.com/irusanov/nForce2-bios-mod

Edited April 11, 2020 by I.nfraR.ed

[digitalbath]

Nice, to see people still working for that socket a platform!

As far as I see, secondary timings, tREF, superbypass, data scavenged rate are fine! I never looked at the primaty timings, but they should be also fine. The second register in b0d0f1 / 94  skips any changes and leaves it at 0.

As for the CR and auto precharge value, i didn't find it in the registers on my Delta2 Setup.

 

I noticed, the Value in b0d0f4 Register 90-9F changes permanently. The Values seems to depend on the Vdd Voltage.

 

[I.nfraR.ed]

You can try if it reads correct timings. Currently I've only implemented read and refresh which re-reads the timings again.

I'm mostly getting these by changing a value on a running system and detecting changes in rweverything.

As for Command Rate I'm not 100% sure it is correct, have to check it on a DFI board. It's read-only anyway.

Yes, 90-9F is some sort of a "sensor" - values go up and down. Perhaps some voltages readings.

You can actually set vdd, vdimm and FID with 8rdacore app on the fly, since it has ATXP1 control implemented.

 

PS: Btw, I'm able to change CAS on the fly! Not sure how effective it is, but at least cpuz detects the change.

Debug.zip

Edited April 11, 2020 by I.nfraR.ed

[digitalbath]

I will try it on my Delta2 / A7N8X-E to check if it reads the right timings.

changing CAS in Windows is impressive! I believe, there is only one possible way to check it: set CAS 3 with Winbond RAM?

 

EDIT:

Command Rate seems to work perfect an both board. The other readings are correct.

 

nice to see that my BIOS also works for you. I think the romsips presets help boards that can't clock as high as yours. My AN7N8X-E ends at 260MHz. The board will not clock higher with more voltage or other romsips. The Romsips presets should also help with memory ICs that normally runs poorly on nForce2.

Edited April 11, 2020 by digitalbath

[I.nfraR.ed]

CH sticks work with CAS3, BH are the ones that don't. I've tried to set 3.0 with a BH-5 stick and it didn't freeze. There's no difference in Pi, so I can probably only use it to detect current CAS. Changing CAS requires setting 3-4 other registers as well, I think. Will keep digging.

[digitalbath]

Good luck with that!

the post in the nForce tweaker thread says:

To change from CAS 2.5 to CAS2.0 you must change this Offsets

PCI Bus#0 Dev#0 Func#1 Offset#

Offset 71 = 24 to 04
Offset 75 = 24 to 04
Offset 9A = 76 to 65
Offset A0 = 6A to 2A
Offset A8 = 6A to 2A
Offset B0 = 6A to 2A
Offset F9 = 46 to 45

On my delta2 board some values are diffrend. By changing one value my system crashes.

delta2
PCI Bus#0 Dev#0 Func#1 Offset#

             cl2,0   cl2,5  cl3,0
Offset 71 =    04      24     04
Offset 75 =    04      24     04
Offset 9A =    54      65     65
Offset A0 =    2A      2A     A2
Offset A8 =    2A      6A     3A
Offset B0 =    2A      2A     3A
Offset F9 =    44      45     45

 

[I.nfraR.ed]

Yes, I have the same values as you. Only 2.5 -> 2.0 worked.

Offset 70 and 74 (dword) bit 13 in each is Half Latency toggle. A0, A8, B0 and B8 bits 6, 5 and 4 are CAS - nforce2 supports 4 DIMMs, but B8 gets ignored in most of the boards since it's not connected. There's at least one Gigabyte board with 4 memory slots, though.

 

[I.nfraR.ed]

I've implemented a temp function which sets all these based on the selected CAS dropdown value and made some tests:

Maybe we need a different sequence or set even more registers in order to make it work for all cases.

Or it's just not possible.

PS: 9Ah and F9h depend on the FSB as well.

 

 

Edited April 12, 2020 by I.nfraR.ed

[digitalbath]

As far as i see, register 70+71, 74+75, 7C+7D, 99, 9A, 9B and F9 depends on FSB speed an CAS Latency. I have no clue what the values means.

Changing one register in 71 / 75  (bit 13 in 70/74) and the system crashes.

 

[I.nfraR.ed]

First usable version. It's still a debug build, but you can use it for setting all the usual timings + tREF.

I've disabled CAS and will remain that way, unless I found a reliable way to set it.

No vendor and device check yet, so you can run even on your shiny new Ryzen under Windows 10

System requirement is .NET Framework 2.0.

 

nForce2XT_Debug_20200416.zip

Edited April 15, 2020 by I.nfraR.ed

[Tzk]

That last build of NF2 XT works as expected on my A7N8X. You could add the other settings aswell. So DriveStrength, Slewrate, Romsips (only the confirmed ones), Data Scavenged rate etc. I guess that's idea behind the 2nd tab on the tweaker? Also: what about using only a single tab, just like A64 tweaker. That way you don't have to open the tweaker twice to show all settings at once.

I've ported @digitalbaths romips tweaks to the non-E Deluxe v2.0 and i'm currently trying to get 2x512mb TCCDs stable above 240Mhz. Let's see if that turns out to be a FSB wall of my board...