zeropluszero Posted September 12, 2019 Share Posted September 12, 2019 Tite. Wouldnt try to do hypers at 7-6-6 or 6-5-5 instead of PSC? Can you kick in that 56x multi for 32M? my old one I think i had to boot 1c1t to get it to jump from 55 to 56 booting. which is less than ideal for 32m but probably still ok. Quote Link to comment Share on other sites More sharing options...
unityofsaints Posted September 12, 2019 Share Posted September 12, 2019 8 minutes ago, zeropluszero said: Tite. Wouldnt try to do hypers at 7-6-6 or 6-5-5 instead of PSC? Can you kick in that 56x multi for 32M? my old one I think i had to boot 1c1t to get it to jump from 55 to 56 booting. which is less than ideal for 32m but probably still ok. Yeah all solid tips. Hypers will do better for sure and 56x multi will set but doesn't complete. Probably heat-related. It's a good chip so I don't want to kill it by going above 1.65V on chiller. Will get the LN2 treatment soon-ish. Btw I had a few runs on Win 7 on 6 min 10 pace hang on loop 24 so the O.S. is definitely wankered. That's why I'm not spending any more time on it for now. Quote Link to comment Share on other sites More sharing options...
zeropluszero Posted September 12, 2019 Author Share Posted September 12, 2019 yeh all good. keen to see what you can do :) Quote Link to comment Share on other sites More sharing options...
yosarianilives Posted September 13, 2019 Share Posted September 13, 2019 Hypers are weirdly bad on sandy, I think that the bioses don't have subtimings set correctly for them. I've even seen where psc just inexplicably scores higher than hypers despite hypers appearing to overall being set tighter. Quote Link to comment Share on other sites More sharing options...
TerraRaptor Posted September 13, 2019 Share Posted September 13, 2019 I remember hypers required high latency boundary to work - killing the performance. Quote Link to comment Share on other sites More sharing options...
Crew Leeghoofd Posted September 13, 2019 Crew Share Posted September 13, 2019 Hypers are ideal on P67 chipset boards, Z77 is not optimal (at least comparing Maximus IV versus V, 4dimms rule in efficiency clock per clock Quote Link to comment Share on other sites More sharing options...
yosarianilives Posted September 14, 2019 Share Posted September 14, 2019 On 9/13/2019 at 12:15 AM, TerraRaptor said: I remember hypers required high latency boundary to work - killing the performance. Indeed, this was my problem on mve Quote Link to comment Share on other sites More sharing options...
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