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Posted

hey zen, did you do a power cycle? it is now required, and if you don't it messes with a few things. Ill try out F5M to see if I have that issue with the dividers too.

 

F5M isn't a progression of anything other than F5j with extra vcore, that is all it is supposed to be.

Posted (edited)

tried just about everything. f5m looks like it was built from f5f based upon the the way the ddr voltage screen looks.

 

up7 has soo much potential, but its held back by bios. 1 (really) good bios could be a game changer.

 

can verify stasio is correct, furthest slots work best. f5j, psc will run to 2580 on 1,3 and 2620 on 2,4. i havent had the up5 in the rig for a while now. mabye its time to throw it in and finish up a software project ive been working on.

Edited by zeneffect
  • Crew
Posted (edited)
up7 has soo much potential, but its held back by bios. 1 (really) good bios could be a game changer.

 

In fact that's my end phrase for the GB Pr contact, great board but bundled with a mediocre bios... darn and the FM2 board is brilliant

Edited by Leeghoofd
Posted
Both the Z77-UD5H and the Z77-UP4 couldn't run XMP timings on my 7-10-7 ripjaws. Needed 8 CAS. Never did figure out what the problem was.

Other z77 boards (ASRock professional, TZ77XE4) could do it fine. One other couldn't (asrock extreme6) and needed the same +1 CAS.

 

Just a heads up really as both boards have been rage-sold at this point :D

 

what's your Ripjaw X.M.P? which model?

Posted (edited)

If I have default Vdimm 1.524V in BIOS "MIT Current Status"......dram voltage didn't work (ET6 and GTL show crazy numbers).

Exchange two stick in the same channel (or sometime different) and getting default Vdimm 1.536V in BIOS MIT section......dram voltage work OK.

 

This also happen on my first board Z77X-D3H since first days.

Edited by stasio
Posted
I I have default Vdimm 1.524V in BIOS "MIT Current Status"......dram voltage didn't work (ET6 and GTL show crazy numbers).

Exchange two stick in the same channel (or sometime different) and getting default Vdimm 1.536V in BIOS MIT section......dram voltage work OK.

 

This also happen on my first board Z77X-D3H since first days.

 

are you mean, after you change the slot with your memory, then the voltage can be adjusted with F5m?

Posted (edited)
can you set manual tRP 8, vdimm 1.65v other timings like I mentioned at first page

CR 2? is CMD you talk?

 

Manual,no problem (XMP wrong)...yea CMD.

btw,same report send to Dino,Colin and Sin long time ago.

Only right CMD (1) with XMP ,I had with BIOS F6x for UP5.

 

are you mean, after you change the slot with your memory, then the voltage can be adjusted with F5m?

 

This is my observation (and it's works) with D3H and UP5.

Sometime clear CMOS also help.

Edited by stasio
Posted
Next Beta BIOS and more errors than with previous one?:confused:Still waiting for good BIOS for LN2 and PSC:(F3OC is still best BIOS for LN2 OC but not for mem clocking...

 

this was a kind of one off bios based upon overclocker requests. in no way was it expected to be stable or have all features work.

 

sin, can you dump your spd and send it to me? i want to compare against mine to see if there is any diff (i doubt it) these issues and your comment are making me doubt my sticks.

Posted
the Kingston 2666C11 you mean? Sure I will make a video too. lol. With F5J i just tested.

 

dont need a video, just the spd dump... but if you WANT to make a video... load xmp boot windows run 32m. i can get the xmp working to a degree with f5j but will fail 32m. this is why im doubting the sticks now.

  • Crew
Posted

had to switch to BBSE for 05 today

 

was behaving same as samsung during benching

 

for this run i was using

 

1.88vdimm

 

8-11-7-26

auto

4

4

8

auto

88

4

16

1

auto

auto

 

tertiaries at auto!

 

image_id_881711.jpeg

Posted

PSC was never improved - not sure if it'll ever be good on the UP7. I posted this screenshot somewhere else already too, but here it is anyway: DDR3-2800 divider with Corsair 2800 memory working on UP7.

 

Now - I must say that when testing F5f for the first time I still had the 15-03-15-15-51 boot cycle too. I got it working by just adjusting:

 

- ddr multiplier

- pll override enable

- change vddr if needed

 

After the first successful boot I could change all settings.

 

13120-45002.png

Posted
dont need a video, just the spd dump... but if you WANT to make a video... load xmp boot windows run 32m. i can get the xmp working to a degree with f5j but will fail 32m. this is why im doubting the sticks now.

 

Let me test this for you, XMp worked fine on this kit, but i think I also suspect maybe it wont pass 32m. I gotta try it out when i toss the Up7back ont he bench. I am super busy these past few days, and I go on a long vacation tomorrow.

Posted
PSC was never improved - not sure if it'll ever be good on the UP7.

 

I certainly hope it will....!

BTW; Once again, thank you le cookie, for listening to the community, its much appreciated that you take note of feedback and allow Gigabyte to work on it.

We've had quite an era of "its your fault" by another staff member, also present in this thread ;)

Posted (edited)
dont need a video, just the spd dump... but if you WANT to make a video... load xmp boot windows run 32m. i can get the xmp working to a degree with f5j but will fail 32m. this is why im doubting the sticks now.

 

Find the KHX26C11T2K2/8X SPD attached. :)

 

(just replace .txt by .spd)

Edited by marmott

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