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CL3P20

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Everything posted by CL3P20

  1. *maybe new wrapper could identify physical # of cores on CPU.. and 'remove' thread count selections that would produce a bugged result. Seems if we could remove the ability to select sets like this from the start, based on current CPU... these bug runs would be minimized quite a bit... @ leeghoofd - I dont have a full proof method for this bench producing a valid score. It takes trial and error after error unfortunately. This is what I have found to work best for this bench though, to produce valid scores efficiently: Use 'no affinity' setting in bench Use the 'Auto' settings, choose your fastest SSE instruction set.. Start with 3 -4 different thread count settings, which are evenly divisible by the physical # of cores your CPU has Re-run using only the 2x fastest thread counts from previous... For valid result the password checked column must "descend" from top to bottom, increasing in the # of passwords checked. As for tweaking for final score : *finding the right combination of thread sets to run for max score is key (even if '64' is your fastest set.. you can boost score using different thread set before or after) *adding 'start /high /b' seems to do little to nothing on a consistent basis for me *using other start flags only increased chance for bug result.. and did NOT increase overall score when run multiple times with/without flags *running my fastest thread set last, with a previously slower set - often gives me a nice boost for overall score (so long as result is valid according to 'password checked' column *Vista for best results vs. Win7 or XP UCBench air G3258 - http://hwbot.org/submission/2582281_cl3p20_ucbench_2011_pentium_g3258_693.4_mpt_score UCBench cold 4670k - http://hwbot.org/submission/2547957_cl3p20_ucbench_2011_core_i5_4670k_1500_mpt_score UCBench cold i7 930 - http://hwbot.org/submission/2547368_cl3p20_ucbench_2011_core_i7_930_1101.1_mpt_score
  2. CL3P20

    up1641

    could you post pic? .. also - what PCB rev# your card?
  3. CL3P20

    up1641

    Try looking for similar IC.. the UP series used has many 're-badged' versions which are the same.. just different name. *some info here -> http://forum.hwbot.org/showpost.php?p=316223&postcount=148 *1641 is 2x phase IC.. you modding VTT or something other than GPUv? Surely your PCB doesnt use 1641 for GPUv... ?!
  4. After some more testing.. I see different results than anticipated. Raising IO comp is choking latency Lowering IO comp is allowing lower latency Raising RTL Init is choking memory bandwidth at current RTL setting Lowering RTL Init is boosting memory bandwidth at current RTL setting
  5. My understanding of it is that; IO Comp is like a 'skew' of tIOL .. like additive latency. Lowering IO Comp, may eventually result in having to loosen tIOL. *try to compare bandwidth/latency against: IO Comp @ 21/22, tIOL @ 1 vs. IO Comp @ 15/16, tIOL @ 3
  6. *random GPU with no available BIOS support from manufacturer - sure we all understand the complications involved in supporting numerous types of GPU design... but 'we' didnt pick it.. *contest class based on unavailable CPU - MSI have no idea of retail availability... ...really...?? I like the benchies.. but really..how to participate when binning GPU is useless and CPU are not available for 1/3 of the comp time? This smells like MSI of past.. 'when something so right..can be sooo wrong'
  7. MSI 750 should use up1608 for VRM .. some rev PCB actually have 4x phase.. newer revs are coming with 4x phase missing ;( Not sure what designates a full fledged 4x phase card.. but seems hit or miss with PCB rev 2.0. *PCI-E connection can be added easily *vmem is single phase - GS9208B : FB = pin20 http://www.gstekic.com/product_detail.php?product_id=63&product_major_id=15&product_item_id=22 SKHynix should do well
  8. Nice work Schmuck! Drop tRAS and squeak another point out for 9th!
  9. yeah.. it traverses the mobo in the opposite direction.. making it cumbersome to use. I have one for my Dimas.. never used it.
  10. moose - Auto produces bug runs the most due to the core/thread formula Geni posted.. run only 2x thread sets no affinity set manually select SSE type
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