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noizemaker

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Everything posted by noizemaker

  1. if you are in europe i have an impact viii for sale.
  2. RKL OCTVB Preview Bios ROG-MAXIMUS-XIII-APEX-ASUS-0020.rar Guide: rkl_octvb.docx
  3. ROG MAXIMUS XII APEX 2201 BETA BIOS ROG-MAXIMUS-XII-APEX-ASUS-2201.7z
  4. on cometlake 50/50 ambient ok, on rocketlake you need cold cpu for 50/50
  5. you need usb drivers, have a look at the apex xii forum
  6. usb stick needs to be fat32 important for APEX 12 Motherboard filename -> M12A.CAP for APEX 13 Motherboard filename -> M13A.CAP
  7. no copy file M13A.CAP on usb stick (fat32) put in USB below LAN Port on the Backside of Motherboard press the Bios Flash Button on the Backside of Motherboard than you can flash
  8. he really did a great effort in binning i just played hope some 8ghz gem appear in Tagg's Intel lots
  9. If you mess up the microcode patches here the bios slot is corrupted, also q-flash restore doesnt work then. you need to flash it via the SPI Header, and if you unlucky you cannot restore MEI anymore. i experienced it on m12a and m13a so be carefully -- if someone cannot start the board or experience with QCODE 00/79/05 and it stuck attach your SPI Header, set Jumper on desired slot and flash latest retail again
  10. Reserved for more Stuff/Guides. --- There quite a few significant changes, however and below is a list that compares traditional expectations vs actual behavior of RKL: Traditional Expectations Actual RKL Behavior Memory and controller can only run in synch Memory and controller can run 1:1 or 1:2 Both odd and even DRAM ratios work Only DRAM odd ratios work for higher frequencies 100:100MHz base DRAM Ratios work as well as 100:133MHz base DRAM Ratios 100:100MHz base DRAM Ratios are significantly worse than 100:133MHz base DRAM Ratios The cores share the same PLL and thus at any point of time, they share the same frequency The cores have their own PLL and thus at any point of time, they can run different frequencies AVX offset is referenced against the all core active ratio AVX offset is referenced against each individual core's ratio limit The voltage needed to run stress tests is more than sufficient for cache to switch ratios High Cache Frequencies require a much higher voltage to switch to that ratio than to run stress tests Even with ring-down bin enabled, Cache will pretty much run up to it's fused max ratio Due to the above, the VID for cache is so much higher than it's core counterpart that often the Cache VID would exceed core's and induce more down-binning since Cache would regulate its frequency to not exceed core's VID requirement. The Memory controller for Rocketlake is significantly different with new features and new limitations. Firstly, there are 2 “Gear” Modes the Memory controller can run in. 1:1 or Gear 1 means that the Controller and Memory clock is in synch. 1:2 or Gear 2 means that the Controller runs at 1/2 of Memory clock. Typically, the controller can maintain a 1:1 mode till about 3600MHz. After which it can no longer work reliably and needs to switch to Gear 2. Since the controller runs at a higher frequency in Gear 1 even if memory frequency is lower, the SA voltage required is thus higher for the same memory frequency. Our auto-rules try to maintain the 1:1 gear mode frequency until 3600. Related to this, since the controller runs at only 1/2 clock in Gear 2, the command rate by default in Gear 2 is 1T, and all sub timings such as Round Trip Latency and turn-around times are tighter in Gear 2. (btw, IO latency timing option is non-existent on RKL) This tries to make up for the latency associated with 1/2 clock. On top of this, there are 2 limitations in Gear 2 mode. This first one is that there are no odd ratios available in this mode. So for example there is no 41.33 ratio. The second limitation is that ratios based off BCLK:DRAM ratio of 100:100 are more unstable compared to ratios based off BCLK:DRAM ratio of 100:133. We have explained this in the help string and have set the non-recommended ratios in grey font. There are 2 VCCIO voltages for RKL. VCCIO Mem OC Voltage is the rail that would need to be raised during overclocking Memory. Typically in the range of 1.25~1.45v. CPU VCCIO voltage at default of 1.05v powers everything else. Another note is that the PCH is powered by a VCCIN of 1.8v which is used as it’s FIVR input voltage. - LN2 The dual 8 pin power connector on M13A has priority differences, the one towards the left is the primary and has to be plugged in. We experienced no Coldbug or Coldbootbug on RKL, so there is no RSVD switches needed As before on Z490 all you got to play with is vcore, sa, io/io memoc and pll term. As starting point set the LN2 Jumper on Mainboard, cool down to -80C Basic LN2 Settings are: Ratio 55 Cache 45 Vcore: 1.65 - 1.75+ VCCIO: 1.30 VCCIO OC: 1.50 VCCIO SA: 1.40 - 1.50 PLL Term: 1.60 - 1.70 Ring PLL Voltage: 1.05 / Auto Internal PLL Voltage: 1.05 / Auto PLL Bandwidth: 2 (higher blck maybe higher) -- Worktool Usage High Cache Frequencies require a much higher voltage to switch to that ratio than to run stress tests. So for example if you’re dynamically switching the Cache ratio in the OS, whether due to power saving or manual adjustments, to switch to high cache you need to set high VCore first to succeed in the switch. Once the ratio is switched over however, the voltage can be lowered significantly, for example you may only need to use 1.7v for cinebench but need to switch to the high ring ratio with 1.90v. The tool does it for you when you apply Fixed Ring Ratio, it well set high vcore before switching, then switch then lower vcore back to previous value. The cores perform slightly differently as the same frequencies, with the middle cores yielding best performance and the first or last being the slowest. If the processor’s favored cores are at the front or back, the single thread performance maybe slower than a processor with favored cores closer to the middle. 1. Put in your desired Ratio - 55 for example 2. Put in your desired Cache Ratio - 50 for example 3. Apply Core to switch CPU Ratio 4. Apply Ring to switch CPU Cache You can try "Maxout all Limits" after you set everything, this max out the Board/CPU Limits if something in Bios is forgot to set. -- XP Tool For XP and Ratio changes you need the attached XP Tools. -- Tools - Worktool https://www.dropbox.com/s/yo5n36kj3xmb6l5/OCTool1221.zip?dl=0 - TurboV Core 1.10.12 (590 and z490) https://www.dropbox.com/s/qfzmx3uvx7ib2xd/TurboV_Core_1.10.12.7z?dl=0 - MemTweakIt https://www.dropbox.com/s/kjowe9faml7e6xh/MemTweakIt.exe?dl=0 -- Legacy Tools - WinXP Ratio Tool https://www.dropbox.com/s/805ioagux8inbqz/xptools.zip?dl=0 - 590 ACPI Files (credits go out to OGS) https://www.dropbox.com/s/ixh046p92cc8pwf/winxp_acpi.zip?dl=0 -- BIOS 0903 BETA ROG-MAXIMUS-XIII-APEX-ASUS-0903.7z 0902 BETA https://drive.google.com/file/d/1osCYx94vY4vu2en_XFES2xDGOOhEsZLY/view?usp=sharing 0901 BETA ROG-MAXIMUS-XIII-APEX-ASUS-0901.7z RKL OCTVB Preview Bios ROG-MAXIMUS-XIII-APEX-ASUS-0020.rar Guide: rkl_octvb.docx 0801 https://drive.google.com/file/d/1TixpPAyQ1oIom_FNmWOv5qI4ex91hOeX/view?usp=sharing 0705 https://www.dropbox.com/s/qz2dw2r2lxic8iv/ROG-MAXIMUS-XIII-APEX-ASUS-0705.CAP?dl=0 0706 https://drive.google.com/file/d/1C5Bt7CmfgLPt7u3HbyN5MV-nzmIQv5yV/view?usp=sharing -- BIOS FOR SUPERPI 0070 (beta) https://drive.google.com/file/d/1SRhK0Jk0XqZkOjJ2X97VP2UgnOSUzNap/view?usp=sharing This is an old BIOS, so it is recommended to use it only when running SUPERPI. Because the latest BIOS has better performance 0062 (beta) https://www.dropbox.com/s/jul8s6col0ownsp/ROG-MAXIMUS-XIII-APEX-ASUS-0062.rar?dl=0 Some refinements to gear 1 , in particular cmd rate 1t mode , plc check if helps!! I use 1.45v io mem and 1.6v SA for 3866 1t just to rule out voltages -- BIOS FLASHBACK PORT Red marked is the BIOS FLASHBACK PORT, Rename your File to M13A.CAP before flashing. -- SPI HEADER FLASH Set the Jumper(blue) left for Slot 1 or right for Slot 2 .ROM BIOS FOR FLASH This Bios is withouth the UEFI Header so you can flash it only via SPI Programmer. https://www.dropbox.com/s/s53p7opjshbfeij/ROG-MAXIMUS-XIII-APEX-ASUS-0801.rom?dl=0
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