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A7N8X-E Deluxe as an alternative for socket 462


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Sure! I basically open the bios with a hex editor (in my case HxD https://mh-nexus.de/en/hxd/) and copy the BPL or romsip tables from one bios to another. You'll find the BPL at offset 70000 to 74BF0 and the romsips at offset 74c00 to 74FF0. Just copy the whole block from one bios to another. Make sure to either choose a bios with CPC on or off as the BPL tables are different.

If you need other romsip or BPL tables, you can just use any bios or modbios, extract, copy and insert them. I even copied from abit to asus without issues. If you want to know which BPL version is inside a bios, you can search for it (just search for "3." or "2." in your hex editor). Usually you'll finde something like:  VDAMC/09/08/2003/v3.19 which would indicate BPL 3.19.

Edited by Tzk
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I'm not an expert when it comes to bios modding... So that might be true ;) I also just discovered that i'm having issues with my files not being fully flashed to the board. If i backup the bios it differs from the file i flashed before. Looks like my romsip tables aren't properly written and that might be the issue why i'm stuck at 240MHz.

I'll now try another way of flashing the board, maybe that'll make a difference... Been using winflash 1.94 till now. So please take what i wrote above with a grain of salt... I'm still experimenting and trying to get on top of my issues.


So looks like you actually can just put the BPL in with a hexeditor. But for the Romsips you need modbin trickery and checksums. This seems the way to go:


extracting the Systembios modul from the bios file, then modifying it and we'll need modbin (preferably the lovelust modded one) to put it back afterwards. However i couldn't find the lovelust modded version anywhere, so i currently can't mod the romsips.


Edited by Tzk
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Just wanted to add to this:

You're correct on the BPL's, you can C&P those without issue. The romsips you cannot. There is checksum involved. You need a dedicated W98 machine to do this. VM will not work.

I use an old P3 W98 box when I mod.

Modded Modbin is not necessary, it just saves you a ton of typing.

Modbin 6 works.


Edited by Mr.Scott
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Seems like you're familiar with bios modding... So, i figured it should work like this:

  1. extract systembios module with either awbedit or modbin6 (even works with win10 64bit)
  2. change romsips in systembios module with hexeditor (again win10)
  3. open bios in modbin (again) and while open replace original.bin with modded module (?)

However i'm not sure how i'm supposed to overwrite the original.bin while modbin is open. CMD in winxp won't let me as the access to the original.bin file is obviously blocked... Or can i just use cbrom32 for this task?! Is there a reason why i need a dedicated win98 machine and VM won't work?

Edited by Tzk
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At least i can tell you now which BPL and Romsips you used on your AN7 1T bios, Infrared. My guess is BPL 3.02 and the Merlin "EB ED" Romsip tables which he used for example in the "D27_TaiPan_0.2_EB_ED_Bpl_3.19_16.12.04" bios for the NF7.

I'm currently trying the two ways Tictac suggested over at XS, however to get a win98 machine running seems to be difficult...

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Yes, based on the filenames I've used EB_ED for AN7 and ED for NF7, however I remember trying some custom tables as well.

I think the best approach would be start from scratch, test which is the best bios for ultra-b, then get the romsip tables and bpl. I will search for my files and tell you how to make 2T bios. I remember saving a screenshot of the hex changes needed.

PS: I've probably used customized ED tables, but not 100% sure.

Here's the BPL (3.02) 2T screenshot I have:


My bioses shouldn't be taken as the single source of truth :D You can probably make a better mod and get better results.

That's what I've accomplished by testing many combinations for stability and efficiency on my boards, which doesn't mean is the best possible one.

I've also never made a bios variant for maximum FSB with poor efficiency, so this might be an interesting thing to explore. I've done 276MHz dual channel "tight" timings, but only for validation/screen, however my AN7 is unstable above 268MHz for benchmarks. Have to try if the registers @TerraRaptor shared, would help with stability above this FSB.


Edit: I also have the SATA/RAID ROM updated to the latest 4.4.02, but usually use a IDE->SATA external adaptor.

Edited by I.nfraR.ed
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I've already tried second method described by TicTac here (using cbrom adding/removing modules): http://www.xtremesystems.org/forums/showthread.php?41261-nForce2-ROMSIP-Table-Mod-Guide-by-tictac

However i'm probably doing something wrong. Here's my current workflow for the A7N8X Deluxe v2.0:

  1. extract systembios module (128kb uncompressed) with awdbedit from bios file
  2. paste romsips obtained from another bios into systembios modul with hexeditor
  3. use the command described by Tictac to paste the modded systembios module into the old bios file (cbrom an7.bin /other 5000:0 system.bin )
  4. cbrom1.98 will generate two temp files during add: original.tmp and bios.rom (i guessed that bios.rom is just the compressed systembios from above)
  5. i now use another unmodded bios file to extract and remove all other modules from it, using cbrom 1.98 in winxp cmd.
  6. i open the emptied bios file from step 5 in a hexeditor and replace the systembios module with the content of the bios.rom obtained in step 4
  7. now readd all modules to the bios with the modded systemmodule
  8. according to tictac cbrom will take care of the checksums
  9. Flash and test!



I have to correct myself. The method described here DOES WORK! ( :D ) Seems like i made some copy/paste errors when i tried this before. I now have the TicTac Mantarays XT D26 romsips working on my A7N8X with BPL3.04 1T. Bandwidth and latency obviously got worse. AIDA64 results with 200Mhz x 6.5 CL2-2-2-11:

1008mod3: read 3000, write 2826, copy 2828, latency 82.5ns

1008+mantaXT (cpu interface "off"): read 2881, write 2545, copy 2682, latency 92.5ns

1008+mantaXT (interface "on"): read 3027, write 2825, copy 2818, latency 82.4ns

1008+TaipanED (interface off): read 2998, write 2822, copy 2807, latency 83.3ns

1008+TaipanED (interface "on"): Freeze during boot

1008+TaipanEBED (interface off): read 2976, write 2547, copy 2700, latency 90.9ns


The Merlin ED romsips did the trick. A quick test gave me 255Mhz 32M and 260Mhz Valid. I'm probably running out of VDimm... Haven't checked efficiency yet.



Edited by Tzk
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Both Merlin Romsips gave me exactly 255MHz (32M stable) and 256Mhz (unstable, but will run 1M) with cpu interface off. However the bandwidth suffers a lot with EBED. I guess for now the ED romsips are perfect to max out both my ram and the board. Also 255FSB on a A7N8X is a great result. I haven't tested different romsips yet.

260Mhz Valid: https://valid.x86.fr/s84l47


Edited by Tzk
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Romsips are the same in 1008mod3-1T for the A7N8X Deluxe and the 1013-1T for the A7N8X-E Deluxe: 6/19 from DFI beta bios. BPL is different though (3.04 to 3.17). I've tried using different bpl (3.17 and 3.19) with dfi 6/19 romsips, but it had almost zero effect. I'll retry with the ED romsips and different BPL. Also setting the cpu interface to enable ("aggressive" on Asus) made my FSB suffer by ~10-15Mhz which is a lot.

I can bench above the "wall", but it's not rockstable anymore. My current conclusion is that i get almost the same latency and bandwidth with 6/19 and Merlin ED, but the latter results in 15Mhz higher FSB, so 240 vs. 255Mhz.

I found some information about the romsip table layout on the pcper forums (thanks, TicTac, i guess! :D ):


sama - sama thumb.gif

The romsip layout after some expirement actually like this

1st table : 133MHz disabled
2nd Table : 133MHz enabled
3rd Table : 166MHz disabled
4th table : 166MHz enabled
5th tabled : 200MHz disabled
6th tabled : 200Mhz enabled

ok lets look at last table
21 41 24 00 00 E4 16 18 <- Timing for each multiplier

arrangement from left to right:
11.0 11.5
12.0 12.5
5.0 5.5
6.0 6.5
7.0 7.5
8.0 8.5
9.0 9.5
10.0 10.5

Example setting multiplier 8 timing:

21 41 21 00 00 ED 16 18 <- bootable
21 41 21 00 00 ED 15 10 <- not bootable (exp: Oskar Wu DFI Infinity 1218 bios)

bold value
lower value -> tight
higher value -> loosen


Edited by Tzk
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I decided to give the BPL another go and tested 3.02, 3.04 and 3.19 BPL with my bios. Let's start with bandwidth results, measured at 200Mhz, Multi 6.5, 2-2-2-11-1T. I used AIDA64 as it was fast and reliable. Everything was benched with cpu interface off, as i can't get the system stable with interface on.

3.02: Read 2995, Write 2819, Copy 2805, Latency 82.7ns
3.04: Read 3005, Write 2821, Copy 2815, Latency 82.3ns
3.19: Read 2995, Write 2818, Copy 2804, Latency 82.7ns

So BPL3.04 wins in terms of bandwidth and latency. I also tried the max. FSB. 3.02 and 3.04 had almost zero difference, as both can run 255MHz perfectly stable but lock up at 256Mhz. 3.19 locks up at 257Mhz, so at least a small improvement.


Regarding the romsips: I'm currently testing Merlin EB ED vs. Merlin ED. The only difference bewteen the two is marked in yellow. This causes a significant hit in latency and bandwidth, but also allows for at least 5MHz increase in FSB (255 vs. 260). The idea is now to find a value inbetween E4 and EB (228 to 235 in decimal) to balance bandwidth and max. FSB.

AIDA64 BPL 3.19:

EB ED: Read 2957, Write 2544, Copy 2695, Latency 91.4ns

ED: Read 2995, Write 2818, Copy 2804, Latency 82.7ns


Edited by Tzk
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Btw, DFI Ultra-B/Infinity bioses have 10 tables, not 6 like the rest of the boards. I don't know why.

PS: Looking at one of my romsips, I've copied the 200 table to all other 5. This is how the "soft L12" mod is done.

Using the same table also means cpu disabled will be the same as enabled. I always use enabled, but it's maybe a good idea to have them 3 by 3, so cpu disabled remains functional.

Edited by I.nfraR.ed
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Yeah, i noticed the DFI tables... No clue why they need 10.

I've tested the different romsips further. The Merlin Taipan 0.3 EB ED romsips are stable at 264Mhz, the ED at 255Mhz. Trats 6/19 is stable at 240MHz. In terms of bandwidth and latency trats 6/19 similar to ED. EBED and ED are similar when running at max. stable clock:

EBED (264Mhz): Read 3928 Write 3359 Copy 3564 Latenz 68,8
ED (255Mhz): Read 3859 Write 3597 Copy 3600 Latenz 64,4

I'd probably choose the ED romsips at 255Mhz as read is only a bit less, but write and latency is by far better. The extra FSB doesn't compensate for the loss of the EBED romsips. I haven't testd other romsips or custom yet.

Edited by Tzk
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On 9/18/2019 at 10:25 PM, TerraRaptor said:

To break above 258-260MHz I change 2 registers in b0d0f3 with wpcredit - offset 66 & 68 set to C7. Voltages are Vcpu 1.85v, Vnb 2.05v, Vdimm 3.8v. The system is not stable at these clocks and it took me several attempts. 265-266Mhz are much better.  Another important notice - once you ran into instability you should power off completely, boot once with fsb 100 and then back to high fsb (I boot with 255 and then raise it with clockgen to the desired value with 1.5-2Mhz steps). Booting once with low fsb is essential - seems like chipset resets something inside with new strap.

I have tried to reproduce this result with NF7-S v2 using exact same hardware but no success - system is unstable above 261.5Mhz. 

Good luck all!

Doesn't work for me on AN7. On unmodded board with my modded bios 66 is set to F7, 68 is 66.

Setting both to C7 leads to BSOD when I try to set 245->250. However, setting 66 to 66 and leaving 68 by default (66) allowed me to set 255+ no problem.

Does anyone have socket A bios and kernel development document?

Also, is there any archive with stock DFI bioses?

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There's a server with a lot of bioses right here:

http://bierbude.spdns.org:2302/Mod-BIOS und mehr/

And for LP B there's these, not sure if modded or stock (beta) bios:

http://bierbude.spdns.org:2302/Mod-BIOS und mehr/DFI/LAnparty B/tictac/


Regarding the registers: what exactly does "b0d0f3" mean? Where am i supposed to look at when i started wpcredit? Do i have to change the device? Also: Which version of WCPRedit? I'm currently running v1.4.

Edited by Tzk
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5 hours ago, Tzk said:

Regarding the registers: what exactly does "b0d0f3" mean? Where am i supposed to look at when i started wpcredit? Do i have to change the device? Also: Which version of WCPRedit? I'm currently running v1.4.

b0d0f3 means bus 0, device 0, function 3. It is DRAM Controller, but what are these bits setting exactly I can't tell without a documentation.

PS: These are all modded bioses, I have the archive, but don't have official/beta bioses from DFI/Oskar Wu.


Edit: This is the archive that has most Ultra-B bioses: http://www.lejabeach.com/DFI/BIOS/dfiultrabbios.html

Edited by I.nfraR.ed
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Just to help you out a bit, I've made 3 batch files (for my AN7 bios). You can adapt to your bios.

Saves a ton of time once done for the bios you're working on.


First, run

cbrom bios.bin /d

to see all the modules, so you can adjust the commands.

Extract all (extract.bat)
Extract all modules without altering the bios file itself

cbrom %1 /xgroup 	extract awardext.rom
cbrom %1 /acpi 		extract ACPITBL.BIN
cbrom %1 /epa 		extract AwardBmp.bmp
cbrom %1 /ygroup 	extract awardeyt.rom
cbrom %1 /group0 	extract _EN_CODE.BIN
cbrom %1 /oem0 		extract BSMICODE.BIN
echo 1 | cbrom %1 /vga	extract NV1ABIOS.ROM
echo a | cbrom %1 /pci 	extract NVPXES.NIC
echo b | cbrom %1 /pci  extract 4402.bin
cbrom %1 /logo 		extract AN7-256n.bmp


Release all (release.bat)

This will release all the modules and you will be left with the system bios only

cbrom %1 /xgroup release
cbrom %1 /acpi release
cbrom %1 /epa release
cbrom %1 /ygroup release
cbrom %1 /group0 release
cbrom %1 /oem0 release
echo 1 | cbrom %1 /vga release
echo a | cbrom %1 /pci release
echo b | cbrom %1 /pci release
cbrom %1 /logo release


Compile (compile.bat)

Insert back the modules

cbrom %1 /xgroup awardext.rom
cbrom %1 /acpi ACPITBL.BIN
cbrom %1 /epa AwardBmp.bmp
cbrom %1 /ygroup awardeyt.rom
cbrom %1 /group0 _EN_CODE.BIN
cbrom %1 /oem0 BSMICODE.BIN
echo 1 | cbrom %1 /vga NV1ABIOS.ROM
echo a | cbrom %1 /pci NVPXES.NIC
echo b | cbrom %1 /pci 4402.bin
cbrom %1 /logo AN7-256n.bmp


All batch files accept just one parameter - the bios file name, e.g.

extract AN7.bin


Edited by I.nfraR.ed
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I used a somewhat similar solution, but didn't come up with the idea to pass the filename into the batch file. Very nice solution, thanks!

Now, here's my files for the A7N8X Deluxe v2.0 and A7N8X-E Deluxe. The -E Deluxe files are untested! So if you intend to flash to a -E Deluxe board, please prepare a backup (programmer, 2nd board for hotflash etc), just in case these files brick the bios.

It would be great if someone brave with a -E Deluxe board could report back if these files actually work. And if not, i can remove or fix them.

1008-RS-A7N8X-DLX-v2.zip A7N8X-E Deluxe RS Bios.zip

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That was my intention. Just expect that these files might brick the bios, so you better got a backup plan to hotflash or program the bios. Also note that these files might default to CL3, so bh-5 might not POST on first boot. I usually fix this by using some random Infineon to boot, then apply CL2.5 in bios and swap back to winbond. I'm also curious if the 1/21 bios gives you better stability above 250FSB ;)

18 hours ago, I.nfraR.ed said:

Doesn't work for me on AN7. On unmodded board with my modded bios 66 is set to F7, 68 is 66.

Here's what i get on A7N8X DLX v2.0:

ED Romsips: 66 is F7 and 68 is 66.

EBED Romsips: 66 is F7 and 68 is 66.

Trats 1008mod3: 66 is F7 and 68 is DD.

And here's what i found in the romsips. Left is Trats, right is ED and EBED. I guess i've found b0d0f3 68 ;) b0d0f3 66 might be a line below in column 07. However this is the same on both romsips, so i'm not 100% sure.


Edited by Tzk
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I've tested it already.

Offset 68 = DD is no boot at 250MHz on my unmodded AN7. When set to 66 it boots no problem - everything else the same.

And yes, that's where you change it in the tables. It's not the only difference between both tables, but I'm not sure which one is better.

I wonder what are these at the first line of each table. Abit stock bioses always have C0 C0 C0 C0 in the first table, then 10 10 10 10, 14 14 14 14 and 18 18 18 18.

Some modded romsips have 0C 10 14 14 for all tables, some 18 18 18 18 for all.


PS: Running AIDA doesn't give me significant differences between different romsips. At 10x200 it's about 3098/3147/3098/80.9ns

Edited by I.nfraR.ed
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Interesting. I've had similarities between DFI 6/19 and Merlin [ED] (which is identical to DFI 1/21), but the latter clocked way better. However Merlins [EB][ED] gave me a 8ns disadvantage but a lot higher FSB. The only difference of ED and EBED is in the 0D column and in 05. Everything else is the same.

I can rerun at 10x200 for comparison, as i was testing at 6.5x200 and different multis got different romsips.

Maybe you can propose a better comparison. I just didn't want to run 32m as it takes ages at low clocks (~50mins).

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