A7N8X-E Deluxe as an alternative for socket 462

[Tzk]

At least from my side it's fairly simple: First, i only got Abit and Asus boards and second Hellfire seems to miss a changelog, so no clue what he did on the modbios he released... On LP B he used the 6/19 bios (and possibly also 6/19 romsips). That's what Trats ported to A7N8X in his 1008mod3 bios. I tried it and couldn't make it past 245Mhz 24/7 stable. With Merlin EBED (which is somewhat based on DFI 1/21 romsips) i'm able to reach >255MHz.

So in simple terms: i didn't see any need to investigate the hellfire bioses

 

I grew up clocking NF2 boards and was always limited by my knowledge. That's why i started pushing further as this is what socket A deserves ❤️

Edited November 9, 2019 by Tzk

[TASOS]

You should check at least his latest Rev3 version

Back then along with dfi-street forums , Hellfire was also posting (with an other username) at xtremesystems.org

I am almost certain he was posting logs.

Anyway

Hellfire Rev3 if i'm not mistaken is based on 1/21

[Tzk]

Yep, 3EG Rev3 seems to be based on 1/21. Interestingly Merlin ED and Hellfire 3EG Rev3 is nearly identical... Only a few values are different which improve system stability with multi 10 to 12.5.

EDIT: 3EG Rev3 is identical with Merlin DFI 12/31. So i assume that Hellfire based his bios on DFI 12/31. There's only a tiny difference between DFI 1/21 and 12/31.

I've yet to extract all romsips from DFI official and beta bioses though.

Edited November 9, 2019 by Tzk

[I.nfraR.ed]

I've already checked 1/21 and 12/31 - they are almost the same and the resulting FSB is the same. It might be +/- 1MHz, but they both load windows at 270MHz and also still unstable at that frequency. Perhaps it's just my chipset limit. Even with slacker memory timings and single channel BH-5 it can't go much higher.

I may have found which byte has the greatest impact on FSB, but will do more tests and then share. At least for me, bandwidth numbers don't change, only maximum bootable FSB changes.

Even with a stock 133 table bandwidth at 200MHz FSB is still similar/the same.

Memory registers are fairly simple to get. I will make a PCR file with all of them + slew rate and drive strengths. Timings are B0/D0/F0, offsets 90 to 97.

Edited November 9, 2019 by I.nfraR.ed

[Tzk]

Maybe the setting you've found is some kind of drive strength? Can't be a timing or else it'd probably influence bandwidth. I'm curious what it is PCR sounds great, should make our life easier.

Next i'll try to add the black.bin ISA rom from TicTacs bios to see if it crashes my a7n8x and if it sets the disconnect feature correctly.

[I.nfraR.ed]

Added the known timings in DRAM Controller 1 (B0D0F1). Most are straightforward, except TRAS is controlled with 2 registers.

91:7 controls lowest bit (e.g. 1111 for 15T), while the rest are controlled by 92[2:0]. Also there's not enough space to list all the options for TRFC (32 in total), so I've written just first and last.

Will make B0D0F4 (slew rates, drive strengths and the rest) later, but I will probably need to switch to DFI to test them properly by setting them in bios.

Also have a PCR file for the Host Bridge by Áedán, but I'm not sure if it is right (10DE01E0).

PCR(PCI Configration Registers) Editor / WPCREDIT for WIN32
Copyright (c) 1998  H.Oda!

[COMMENT]=Author: I.nfraR.ed, v.1
[MODEL]=nForce2 
[VID]=10DE:nVidia
[DID]=01EB:Memory Controller

(00)=Vendor Identification
(01)=Vendor Identification
(02)=Device Identification
(03)=Device Identification

(86:1)=Auto Precharge

(90:3)=TRC
(90:2)=0000=0T 0001=1T 0010=2T 0011=3T 0100=4T 0101=5T
(90:1)=0110=6T 0111=7T 1000=8T 1001=9T 1010=10T
(90:0)=1011=11T 1100=12T 1101=13T 1110=14T 1111=15T

(91:4..0)=TRFC 00000=0 ... 11111=31

(91:7)=TRAS = TRAS+1
(92:2)=TRAS 000=0T 001=2T 010=4T
(92:1)=011=6T 100=8T 101=10T
(92:0)=110=12T 111=14T + (91:7)

(92:6)=TRCD-R 000=0T 001=1T 
(92:5)=010=2T 011=3T 100=4T
(92:4)=101=5T 110=6T 111=7T

(93:6)=TRP 000=0T 001=1T 
(93:5)=010=2T 011=3T 100=4T
(93:4)=101=5T 110=6T 111=7T

(93:2)=TRCD-W 000=0T 001=1T 
(93:1)=010=2T 011=3T 100=4T
(93:0)=101=5T 110=6T 111=7T

(94:6)=TRTW 000=0T 001=1T 
(94:5)=010=2T 011=3T 100=4T
(94:4)=101=5T 110=6T 111=7T

(95:5)=TREXT 00=0T 01=1T 
(95:4)=10=2T 11=3T

(95:2)=TRTP 000=0T 001=1T 
(95:1)=010=2T 011=3T 100=4T
(95:0)=101=5T 110=6T 111=7T

(96:6)=TWTP 000=0T 001=1T 
(96:5)=010=2T 011=3T 100=4T
(96:4)=101=5T 110=6T 111=7T

(96:2)=TWTR 000=0T 001=1T 
(96:1)=010=2T 011=3T 100=4T
(96:0)=101=5T 110=6T 111=7T

(97:6)=TDOE 000=0T 001=1T 
(97:5)=010=2T 011=3T 100=4T
(97:4)=101=5T 110=6T 111=7T

(97:2)=TRRD 000=0T 001=1T 
(97:1)=010=2T 011=3T 100=4T
(97:0)=101=5T 110=6T 111=7T

 

10DE01EB.pcr

10DE01E0.pcr

Edited November 9, 2019 by I.nfraR.ed

[Tzk]

Your PCR works as expected. Thanks!

I doublechecked with NF2 Tweaker and this works:

Auto Precharge
offset 0x86h
0Fh = 00001101b = enabled
0Dh = 00001111b = disabled 

And i found+checked these:

			****************************
				* nVidia nForce2 Data Base *
				****************************

1) AGP  Controller Latency
  *************************
	PCI Bus#0 Dev#30 Func#0 Offset#0D
	
		      0D
	- 16  clock : 10
	- 32  clock : 20
	- 64  clock : 40
	- 96  clock : 60
	- 128 clock : 80
	- 160 clock : A0
	- 192 clock : C0
	- 224 clock : E0
	- 255 clock : FF


2) AGP  Bus Latency
  ******************
	PCI Bus#0 Dev#30 Func#0 Offset#1B
	
		      1B
	- 16  clock : 10
	- 32  clock : 20
	- 64  clock : 40
	- 96  clock : 60
	- 128 clock : 80
	- 160 clock : A0
	- 192 clock : C0
	- 224 clock : E0
	- 255 clock : FF
	
	
3) PCI Latency
  *************
	PCI Bus#0 Dev#8 Func#0 Offset#1B
	
		      1B	
	- 16  clock : 10
	- 32  clock : 20
	- 64  clock : 40
	- 96  clock : 60
	- 128 clock : 80
	- 160 clock : A0
	- 192 clock : C0
	- 224 clock : E0
	- 255 clock : FF
	
	
4) CPU Disconnect Function
  *************************
	PCI Bus#0 Dev#0 Func#0 Offset#6C,6D,6E,6F
	
		    6C 6D 6E 6F
	- Enable  : 01 FF 01 1F/9F
	- Disable : 01 FF 01 8F
	
	
5) Command Per Clock (T1/T2)
  *******************
  	PCI Bus#0 Dev#0 Func#1 Offset#84,85,86,87
	
		    84 85 86 87
	- Enable  : F3 13 0F 03 
	- Disable : F3 13 0F 23 
	
	WARNING! (Not Editable after boot, Can only be set before memory sizing)
	
	
6) Alpha Memory Setting
  **********************
	PCI Bus#0 Dev#0 Func#1 Offset#94,95,96,97
	
		    94 95 96 97
	- T(DOE)  :	     x	Selectable Value: 0,1,2,3,4,5,6
	- T(RRD)  :           x Selectable Value: 0,1,2,3,4,5,6
	- T(W2P)  :       x	Selectable Value: 0,1,2,3,4,5,6
	- T(W2R)  :        x	Selectable Value: 0,1,2,3,4,5,6
	- T(REXT) :    x	Selectable Value: 0,1,2,3
	- T(R2P)  :     x	Selectable Value: 0,1,2,3,4,5,6
	- T(R2W)  : x 		Selectable Value: 0,1,2,3,4,5,6
	- reserved:  -		Selectable Value: -
	
	- Offset 94 = XY
		X= T(R2W)	Selectable Value: 0,1,2,3,4,5,6
		Y= Reserved	-
		
	- Offset 95 = XY
		X= T(REXT)	Selectable Value: 0,1,2,3,
		Y= T(R2P)	Selectable Value: 0,1,2,3,4,5,6
		
	- Offset 96 = XY
		X= T(W2P)	Selectable Value: 0,1,2,3,4,5,6
		Y= T(W2R)	Selectable Value: 0,1,2,3,4,5,6
		
	- Offset 97 = XY
		X= T(DOE)	Selectable Value: 0,1,2,3,4,5,6
		Y= T(RRD)	Selectable Value: 0,1,2,3,4,5,6


7) Side Band Addressing
  **********************
	PCI Bus#0 Dev#0 Func#0 Offset#49

		    49
	- Enable  : 03
	- Disable : 01

Source: http://forums.pcper.com/showthread.php?335978-DFI-Alpha-setting-come-in

Edited November 10, 2019 by Tzk

[Tzk]

@Thorn & @Mr.Scott

I updated the DFI LPB Merlin bios. Thorn noticed that i accidentally used the wrong system module (discovery 0.1 instead of 0.3) for the romsip swap. So here's the updated version, this time with a) correct system.bin module and b) changed post message to indicate the romsips. No other changes were made and the bios is untested.

MerlinDiscovery0.3+ebed+ed.zip

You can also find the archive here: http://bierbude.spdns.org:2302/USER UPLOADS/Tzk/DFI/Lanparty Ultra B/

Edited November 11, 2019 by Tzk

[I.nfraR.ed]

Got the Nano Flasher too. Tired of the old Willem programmer that requires LPT port, configuration and external power. This should be much easier to work with.

PS: By the way, does anyone know how to change the colors of the bios?  The modbin option doesn't work, I think it worked for Award 4.xx, but not for 6.00 and I don't know where the colors are hardcoded.

Edited November 11, 2019 by I.nfraR.ed

[Tzk]

Success!

I'm able to change my custom settings in bios, this is then saved to CMOS registers by the bios. Then during boot my custom ISA option rom reads the CMOS registers and sets the corresponding values based on the cmos register.

I still got a off-by-one error i must trace down, but in theory it works. I'm currently setting registers 64, 66, 70, 72, 7E (last register is missing) while i want to set 65, 67, 71, 73, 7D and 81.

Edited November 11, 2019 by Tzk

[I.nfraR.ed]

I have found another version of Award bios editor that shows menu items text (almost) correctly. I don't think it will work for editing, but at least could be used for easier viewing.

http://bios.rom.by/ROMutils/Award/awdbedit/re1_25.zip

On NF7 I only have 5 unused items, I think. So same as on your Asus.

 

Edited November 11, 2019 by I.nfraR.ed

[Tzk]

Afaik every version of AWDBedit corrupts the bios when you save it, at least for Award v6.0PG. Might work for 4.51, though.

When i got everything working on my modbios, i'll upload the code somewhere and write down how i did it. Implementing new items is easier than one might think

Edited November 11, 2019 by Tzk

[I.nfraR.ed]

I only miss how to read cmos registers value, but haven't tried anything about it yet.

The problem is we have 3 drive strengths and 3 slew rates - 2 settings for each DIMM. Then alpha timings, superbypass, scavenged rate.

Did you find how to add more items?

PS: Do you read actual bios value or you set your custom default option for the new items? If not possible, maybe set to "auto" and when ISA custom code reads it's not set manually then don't alter it.

Edited November 11, 2019 by I.nfraR.ed

[Tzk]

I tried to add more settings but still didn't succeed. I haven't tried another time though. So currently i'm working with the unused 5 items i got. It must be possible to add more items as DFI uses 260+ and Asus uses 210+, but i coulnd'd figure out how up to now.

Currently i added custom settings like this:

1. Search the bios for the 5 unused items and rename them
2. Add a new label group and subitems (selectable choices) in _EN_CODE.BIN
3. Make the 5 items point to the subitems in EN_CODE.bin and configure it for the correct amount of choices
4. Configure the mask and (custom) cmos register for the 5 new items, this will write to the desired register when selecting an option in bios

Now we got 5 new items which already have selctable choices in bios and store their settings correctly inside cmos registers. What's missing is code to actually do something. So next up we do this:

1. write an ISA option rom which reads the Cmos register we configured in 4)
2. based on the register value we do nothing (when setting is set to "auto") or set the desired value

That's it. I configured the settings to default to "auto" which will write a zero to the cmos register. This will just jump my custom code and do nothing. For the drive strength i currently use a single setting and register to set 00 to FF (which is 0Fh different choices) and just write all 6 available registers with the same value. I'm not sure we need to be able to set all strengths differently.

I use FASMW to compile assembler to usable binary.

Now, you asked how i read the Cmos register values. Here's my heavily commented code which is based on TicTacs A64 patcher code:

;read drive strength
;this is where the drive strength AND slew rate setting is stored
;i chose the first 4 bits for drive strength and the last 4 bits for slewrate
;so register 75h = 0Fh is drivestrength auto, slew rate 15
;and register 75h = F0h is drivestrength 15 and slewrate auto


mov al, 75h     ;index - 75h, set cmos register index address
out 072h, al    ;send register offset to special address register
in al, 073h     ;fetch data from special data register
and al, 0F0h    ;mask al to discard last 4 bits as these are used for slew rate
cmp al, 00h     ;check if Drive Strength is set to auto and if yes
je slewrate     ;jump to next setting(equal 0000.0000)   

cmp al, 10h         ;check if DS is set to 1
je drivestrength1   ;jump if equal 0001.0000

(....)              ; we check up to 15 as this is the highest possible setting

cmp al, F0h         ;check if DS is set to 15
je drivestrengthF   ;jump if equal 1111.0000

And here's the code i currently use to set the drive strength registers. Note that i'm intentionally not using macros to keep it simple and i'd call this some sort of spaghetti code

;set drivestrength = 11h
drivestrength1:
mov eax,080000464h ; 1st drive strength address for offset 65 and 67
mov ebx,011001100h ; 1st data for 1st address, offset 65 and 67
mov dx,0CF8h ;
out dx,eax ;
mov dx,0CFCh ;
in eax,dx ;
and eax,000FF00FFh ; mask data. removes the old data from eax
or eax,ebx ;
out dx,eax ;
;
mov eax,080000470h ; 2nd drive strength address for offset 71 and 73
mov ebx,011001100h ; 2nd data for 2nd address, offset 71 and 73
mov dx,0CF8h ;
out dx,eax ;
mov dx,0CFCh ;
in eax,dx ;
and eax,000FF00FFh ; mask data. removes the old data from eax
or eax,ebx ;
out dx,eax ;
;
mov eax,08000047Ch ; 3rd drive strength address for offset 7D
mov ebx,000001100h ; 3rd data for 3rd address, offset 7D
mov dx,0CF8h ;
out dx,eax ;
mov dx,0CFCh ;
in eax,dx ;
and eax,0FFFF00FFh ; mask data. removes the old data from eax
or eax,ebx ;
out dx,eax ;
;
mov eax,080000480h ; 4th drive strength address for offset 81
mov ebx,000001100h ; 4th data for 3rd address, offset 81
mov dx,0CF8h ;
out dx,eax ;
mov dx,0CFCh ;
in eax,dx ;
and eax,0FFFF00FFh ; mask data. removes the old data from eax
or eax,ebx ;
out dx,eax ;
;
jmp slewrate ; jump to next setting

 

Edited November 12, 2019 by Tzk

[Tzk]

Doublepost to keep things separated.

Next up i booted the board with stock settings at different FSBs to check default drive strength. Note that Asus seems to set the registers in pairs. We got 6 registers (2 for each Dimm), and Asus sets it like: Dimm1: A B, Dimm2: A B, Dimm 3 A B with A and B being different drive strengths. Results:

• 133 FSB: 55 99
• 166 FSB: 33 99
• 200 FSB: 33 44
• 200+: 33 44 (no change after that)

So now i'm unsure how the options are mapped in bios. On DFI Ultra-D (NF4) the even values were "strong" and the uneven values were "weak". This resulted in a table like this:

(weakest) 7 5 3 1 2 4 6 8 (strongest)

I'm unsure if this is also the case on Socket A. However i'd assume that Asus might increase the strength with higher FSBs. As they go from 55 to 33 and from 99 to 44 it might be the same as on NF4. Maybe someone of you guys knows this...?

[I.nfraR.ed]

Thanks for the explanation, I found how to read the cmos regiser in the pdf you linked before. So I now have the idea how to do it.

As for the settings, sometimes you'd want different values for different DIMMs I guess, but we can work with same set of settings for now. Don't know if they are the same as on NF4 or from 1 to 8.

I also have just 5 free slots in NF7 bios. NF7 sets drv strength at 3 and slew rate at 10 (33/AA) for all dimms at 200+. BPL 3.19 if that matters. Stock is 3.02.

It seems you can add labels at the end of _EN_CODE.BIN, but the question is how to add a brand new submenu with as many items as we want. This might require correcting all pointers of the existing items

Edited November 12, 2019 by I.nfraR.ed

[Tzk]

I chose the following settings for now: Drive Strength, Slew Rate, SuperBypass, Data Scavenged Rate and Auto Precharge. I'm not sure i need the last (AP), but it should be possible to for example set Dimms 1&2 with one setting and Dimm 3 with another setting. You mostly wouldn't run 3 Dimms anyways. Or you could set the first set of registers differently than the others (like Asus did). Or we could add a completely different setting.

I'd love to add all alphatimings, however i'd need to find a way to add extra settings to the bios. The PDF described how you'd do it on a newer bios with ITEM.BIN module, but sadly not for ITEM.BIN-less bios. Just adding a setting to system.bin bricked the bios when i tested this. My assumption is that the code blocks before and after the actual settings are used for the settings itself and thus you can't just add a new setting in the middle.

[I.nfraR.ed]

I don't know if it is possible at all, but one possible way is to somehow add a new module with all the subitems and just use an unused label that points to it and opens a subpage (a.k.a [Press Enter]) - basically a mini bios in the bios. Award bios editor has the option to add a BIOS Setup Menu. But I don't know how to make such a menu.

On a side note, if you want to change the build date and version number of the modded bios file, edit the system bios with hexeditor - search for the date displayed in cpuz. You can find it on 2 places, e.g. the full date 11/11/2004 and the short date 11/11/04. The version number is taken from one of the bios message strings displayed in award bios editor (second one). It seems to split the string with "-" as a delimiter, so last chars will be the version. Then use the cbrom method to compile the bios back.

Edited November 12, 2019 by I.nfraR.ed

[Tzk]

I'd guess that this setup menu in AWDBedit is the ITEM.BIN on later Award bios. This basically splits the bios items and the system.bin in separate files. Just open a later bios (eg athlon 64 or intel socket 775) with cbrom and check if it includes item.bin...

I just tested a few DS settings and it seems 33h is the best settings for Infineon BT-5 (found on Corsair 3200C2). I had thousands of errors when using below 22 or above 88. Probably slew rate needs also adjustments to get the maximum out of these settings.

Edited November 12, 2019 by Tzk

[Tzk]

So... I just finished setting everything inside my option rom up. BUT i think that the SuperBypass register is wrong. Tictac mentioned it at B0D0F4 register 91h. He also mentioned AutoPrecharge and DataScavengedRate at B0D0F4 which both actually are at B0D0F1. Oops...  I located the latter two, but can't find SuperBypass...

Next up is checking if AutoPrecharge, DataScavRate, Slew and DriveStrength work.

EDIT: Everything works. Nice.

Edited November 12, 2019 by Tzk

[Thorn]

Congratulations. Now hopefully all the brainpower and hard work pays off

Edited November 12, 2019 by Thorn

[Tzk]

Well, i'm still looking for SuperBypass... Everything else works and i need to test it with Winbond Sticks. But before trying this, i'll document how i did it and upload the source of my ISA option rom somewhere. So you guys can either do this mod yourself or at least i know in a few months how i did it.

It shouldn't be too difficult to port this to other Asus boards, at least when they also got 5 unused settings in bios.

Edited November 13, 2019 by Tzk

[Tzk]

I investigated the bios item strings in system.bin further and i noticed something. Before and after each bunch of strings, there's some "code". The code before each bunch seems to indicate where the strings start. On Asus the system.bin includes the bios items starting at 10000h, so i assumed that the code doesn't assume this offset. So i copied everything to a new file (10000h offset now gone) and tried my luck.

Note that each bunch of bios items seems to start with 246D 6C24h which translates to $ml$ (marked in yellow).  I then noticed that the immediately following codeblock seems to have increasing numbers following each other. And it looks like that these numbers actually indicate where the bios items are saved. For example the blue box at offset 1ACh has B602h in it which is an address written in little endian (least significant byte first). So we swap bytes: B602h -> 02B6h. And guess what, the corresponding bios item string starts at 02B6h (big blue box at the bottom). This is the same for the other boxes i marked.

I don't know what the numbers inbetween the small boxes do, but they seem to point to the codeblock following after the bios items. So i assume this is a lookup table for the bios items and some other setting.

My current conclusion is:

I tried adding new bios items before and that bricked the bios file. I assume that it broke because i tried to add new items at the start (near initial offset 10000h). This would cause all following $ml$ blocks to have an offset, as i had to insert a few bytes. Now, that'd break all following lookup tables and i'd miss the new item on the corresponding lookup table.

So it looks like we'd need to: 1. insert a new item, 2. add it to the lookup table 3. add the following setting pointing to the end of the segment and 4. correct any offset we broke by inserting some bytes.

But first, we need to figure out what the 2nd codeblock directly after the item strings does.

 

Edited November 13, 2019 by Tzk

[I.nfraR.ed]

Superbypass seems to be b0/d0/f1 offset FC lowest bit.

FC:0 (0000000x)

0 - disabled, 1 - enabled

Will do more tests on the dfi, but drive strenghts and slew rates seem to be right.

b0/d0/f4 row 90 seems to be changing constantly (autorefresh of rweverything shows that), so 91h is indeed incorrect.

Edited November 13, 2019 by I.nfraR.ed

[I.nfraR.ed]

Ok, checked both settings

(F8:2)=Data Scavenged Rate 0=Fast 1=Normal

(FC:0)=SuperBypass 0=Disabled 1=Enabled

b0/d0/f1 Memory Controller 1

Data Scavenged Rate  - offset F8, bit 2; 0 is Fast, 1 is Normal

SuperBypass - offset FC, bit 0; 0 is Disabled, 1 is Enabled

There's one more setting in DFI bios called "Sync Mode Memory Bypass", but the board doesn't boot when set to Disabled. Might be dependant on memory chips or modules installed. Will test more and report back if I find something.

Update PCR file attached.

 

Drive Strength and Slew Rate are correct.

b0/d0/f4

DIMM1 - DS is 7Ch and 81h, SR is 7Dh

DIMM2 - DS is 67h and 73h, SR is 66h

DIMM3 - DS is 65h and 71h, SR is 64h

 

Good thing is I can change all of them (DS, SR, SuperBypass, Data Scavenged Rate) in wpcredit on the fly.

10DE01EB.pcr

Edited November 13, 2019 by I.nfraR.ed