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Everything posted by wytiwx

  1. MAX FSB your mobo and CPU can post on air?
  2. maybe PL10 failed at that time, can't remember well, a few months ago
  3. Is mem bandwidth of 750MHz/DDR3-1500 the experimental results? But in other words, if we have to use 3:5 for efficiency rather than raw mem freq in particular conditions, it doesn't matter whether there is a bug or not.
  4. Well,if FSB and Mem freq is almost the same, then I think mem performance should be strap 400 < 333 <266 < 200. But if FSB and Mem freq scares too much, things will become complicate.
  5. I did some memory bandwith test by AIDA64, I don't think it has 3:5 bug for my EP45T-UD3R 1. E8400 (500x6), 400 strap, div 3:4, DDR3 1333 6-6-6, PL9 2. E8400 (500x6), 400 strap, div 3:5, DDR3 1666 6-6-6, PL9 3. E8400 (500x6), 333 strap, div 5:8, DDR3 1600 6-6-6, PL9
  6. We all know that P45 has memory div 3:5 bug, but I still wonder: 1. Does this bug exist in all P45 boards? For exmaple, is in all DDR2 and DDR3 board? is in all chipset rev. A2 and A3? 2. If not all P45 board have this bug, how can we confirm that when we use 3:5 ?
  7. My percent overclock score is for Intel or for BCLK, the really highest percent is donw by AMD up to 300%+
  8. If you don't have good D9GMH, maybe you can try those crazy nanya d-die just kidding
  9. Crazy mem. Are you really sure the IC is nanya? Have you removed the heatsink?
  10. hahaha, that would be a very big project which need all the OCer s.
  11. Yep, actually two E7200 hit 700 FSB by now, both are Wolfdale-3M, not from Wolfdale-6M
  12. C2D E7200, 730 done, batch Q748A https://hwbot.org/submission/4754186
  13. updated 266 bus speed CPUs which did 700+ C2D E6300, 705 done, batch L632B. https://hwbot.org/submission/4740813
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