Massman

I know what you're trying to do, K404, but we're not going to start a witchhunt to try and track down every single user that got a free hw sample or a nice company contact that gives him better access to certain information. It's not because you get something for free that you are automatically Pro. Moving to Pro is on a voluntary basis if the user feels that he's has too much company contacts to compete in the regular league. Of course, there are exceptions like people who actually work for a vendor (which will be 'forced' to pro) and we're also sometimes contacting people to check if they want to consider moving due to contacts.

We follow the original vendor's guidelines. In this case: if Asus wants to say the Xpander really is a retail product, then fine for us. If Intel says ES is never available in retail, then okay fine for us.

That involves too much work and it doesn't make things much better. Remember F1-OC where Evga made the GTX285 Classifieds "retail" by setting up a (fake) pre-order system?

http://www.overclockzone.com/news/view.php?id=1063

Oh, I just realized it's configured differently. My bad! Stages are based on stock CPU core_count and not on effective cores. Ie: in the 2xCPU category, you can technically use a quad socket system with 4 dual cores . I'll update the frontpage too so it's more clear

I have emails from @asus folks that literally say "xpander is available in retail". I think they were in stores in Japan, or so.

Just got this in my mailbox from a friendly anonymous source. According to source, this BIOS is supposed to be the xtreme OC bios for the reference HD 7970 (just like the 'pros' are using). It would allegedly disable powertune and override CCC limits. - AMD Radeon HD 7970 (reference) xtreme oc BIOS: http://91.121.148.119/downloads/VGABIOS/Tahiti_XT_C3860100_X00_BIOS_Dec20_2011.exe Double-click the .exe and the bios will be flashed on your card. If you tested this BIOS, please provide feedback

Or: memory clock is real

Not artificially, I'm sure that in Intel specs this will be guidelined like this. The explanation is really simple: each memory channel represent 64bit of data. In triple channel, that means there's 192bit of data available each clock tick. The IMC in the cpu is not 192bit width (technical design limitation), so you need to run the IMC faster than 1:1 if you want to transfer that 192bit as fast as possible. All cpus based on Nehalem design are basically the same architecture, but just with different characteristics like # cores and # of adresseable channels. The more cores you have, the more imc width you have, thus the more data you can grab per clock cycle. For a 4c nehalem design and triple channel, the lower limitation is 1:2. Why? 4 cores = 4x24bit imc and triple channel = 3x64bit interface. So, if you have imc at 2x speed of memory, you can adress 2x4x24bit data with 2 imc clks and one dram clk. So: 8x24bit = 192bit and 3x64bit = 192bit too. That is like Bloomfield! For a 4c nehalem design and dual channel (like Lynnfield), the limitation is 2:3. Why? 4 cores = 4x24bit imc and dual channel = 2x64bit. If you have IMC at 1,5x speed of memory, you can address 3x4x24bit data with 3 imc clk in 2 dram clk. So: 3x4x24bit = 288bit and 2x2x64bit = 256bit. In this scenario, you have a bit of "imc clk" left, but that has got to do with proper alignment ("it's easier to split a 192 block in 2x 96 bit than in 3x 64"). You can make the same exercise for Gulftown. All other boards just stuck with the default limitations of Intel spec, but it seems that the X58A-OC board is actually working with all the different combinations as long as the alignment is ok. So, any combination of # cores and # of channels you set has a different ratio limitations. Pretty nice, actually!! //EDIT: Urgh, this does not look understandible at all. Let me try again. For all Nehalem/Westmere family; - 2 cores = 48bit cpu-imc interconnect - 4 cores = 96bit cpu-imc interconnect - 6 cores = 144bit cpu-imc interconnect - single channel = 1x 64bit = 64bit = 2x 32bit (for easy alignment at 1/2) - dual channel = 2x 64bit = 128bit = 2x 64bit (for easy alignment at 1/2) - triple channel = 3x 64bit = 192bit = 2x 96bit (for easy alignment at 1/2) So, for - 2C-TC: 1x 192bit = 4x 48bit => 1:4 => DDR3-2000 must have 8000 MHz uncore (/) - 2C-DC: 3x 128bit = 8x 48bit => 3:8 => DDR3-2000 must have 5333 MHz uncore (/) - 2C-TC: 3x 64bit = 4x 48bit => 3:4 => DDR3-2000 must have 2666 MHz IMC (*) - 4C-TC: 1x 192bit = 2x 96bit => 1:2 => DDR3-2000 must have 4000 MHz IMC (Bloomfield) - 4C-DC: 3x 128bit = 4x 96bit => 3:4 => DDR3-2000 must have 2666 MHz IMC (Lynnfield) (*) - 4C-SC: 3x 64bit = 2x 96bit => 3:2 => DDR3-2000 must have 1333 MHz IMC (/) (*2) - 6C-TC: 3x 192bit = 4x 144bit => 3:4 => DDR3-2000 must have 2666 MHz IMC (Gulftown) (*) - 6C-DC: 9x 128bit = 8x 144bit => 9:8 => DDR3-2000 must have 1777 MHz IMC (/) (*2) - 6C-SC: 9x 128bit = 4x 144bit => 9:4 => DDR3-2000 must have 888 MHz IMC (/) (*2) (*): problem with alignment if you use 3:4 ratio, it's easier to use 2:3 and just leave some IMCclk unused (info). (*2): I guess theoretically you can have uncore lower than memory clock, but I assume there are other limitations that prevent IMC to be clocked lower than DRAM. Maybe related to cache. So, in practice you can't go below 1:1. The above configuration counts for native xCore parts. Most of the combinations were never released. For instance, if they would have made a native 2core Nehalem with triple channel support, they would've needed an uncore part clocked at 8000MHz to support DDR3-2000. Practically, that would mean Intel would've spec'd that part as DDR3-800 max or so (3200MHz IMC). The advantage of a native 6core CPU like Gulftown is that there's always a 144bit IMC present, so can easily run 1:1 with uncore. Does this make sense?

Okay, from what I can distilate from the two screens, it seems that the frequencies are indeed being reported correctly. Actually, it all makes perfect sense. Hint: http://www.madshrimps.be/vbulletin/f39/mass-uclk-technical-limitations-useful-marketing-tool-65573/

Seems like many people are looking for the workaround, but it's hidden too deep in the forums. So, again: Good luck!

Don't use this driver when you run more than 1 card in CF. It freezes up in 2D desktop here. Works fine with 1 card.

Monday. Magic. Muahaha.

Why is the score so low?

pieter@hwbot.org :-)

Once a score is verified, a user can no longer edit it. Just a security measurement .

There's no perfect solution, I'm sure. Guys, please remember that the HOC competitions are mainly for fun and for testing things out. So, I'd like to know what all the people who are against it now, say after the competition has finished. Doesn't matter if your opinion is the same, different or more elaborate ("this is good, this is bad") . Btw, last month we had a another point scheme and Overclock.net won. On their forums, there was actually a thread going with guys discussing how to approach it. So, they had a plan and they won.

If you have the highest score, you get 10 points. Which is the highest amount of points you can win per stage.

- Asus Rampage IV Extreme --- 0005b: download - Asus Rampage IV Formula --- 0005b: download - Asus Rampage IV Gene --- 0005b: download

2600K = 4x CPU

Justice has been served

No. Enabling more cores is allowed; disabling them is not.

Ok, thanks for your approval! :celebration:

- Asrock Fatal1ty X79 Professional --- V1.00: download - Evga X79 Classified --- 030: download - Evga X79 FTW --- 030: download - Evga X79 SLI --- 030: download