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Posted (edited)

I do not have this card. This mod is untested.

 

Here's a closeup of the chip and the MSI card:

 

vreg.jpg

 

Highres Front Image

 

(Thanks TPU)

 

From the images, the VID pins are as follows:

 

Pin 54 - VID7

Pin 55 - VID6

Pin 56 - VID5

Pin 57 - VID4

Pin 58 - VID3

Pin 59 - VID2

Pin 60 - VID1

Pin 61 - VID0

 

These pins on the 1981 are by a double bank of resistors which is how VID is designed. When I refer to the first bank of resistors, I mean the bank closest to the controller (the orientation of the two images is different, so it can get confusing).

 

Here's an updated image:

 

4a97bcc5_vreg_1.jpeg

 

Assuming these pins are the VID pins, here are the values I got from the images of the 560 above:

 

Pin 54 - VID7 0 1 (Bank 1 Bank 2)

Pin 55 - VID6 0 1

Pin 56 - VID5 0 1

Pin 57 - VID4 1 0

Pin 58 - VID3 1 0

Pin 59 - VID2 0 1

Pin 60 - VID1 1 0

Pin 61 - VID0 1 0

 

Note that the first bank of numbers (the resistors closest to the chip) are the ones called out in the VID table. When one bank contains a resistor, the other will not. The 1 represents where the resistor goes.

 

So the two banks above translate into:

 

7 6 5 4 3 2 1 0 (VIDx)

0 0 0 1 1 0 1 1

 

Quick binary tutorial:

 

1 - 0000 0001

2 - 0000 0010

3 - 0000 0011

4 - 0000 0100

5 - 0000 0101

6 - 0000 0110

7 - 0000 0111

8 - 0000 1000

 

Referring to the uPI datasheet attached, you can see that our number (0001 1011) corresponds to a Voffset of 168.75mV. If you measure the voltage that the controller is providing the GPU, you can use this to determine the reference voltage (Vref) for the controller (the voltage upon which all of the VID adjustments are based).

 

Vref = vGPU - Voffset

 

For example, if the vGPU is 1.20V, the reference voltage for the controller is 1.20V - 0.16875V = 1.03125V. Knowing this reference voltage, assume we want a vGPU of 1.50V. To find the Voffset, we would do 1.50V - 1.03125V = 0.46875V = 468.75mV. Looking to our tables, this means we need a VID configuration of 0100 1011.

 

 

 

So you want to perform this mod?

 

Here's what you need to do:

 

Note the stock voltage (under load) of your GPU in Windows. If software voltage monitoring is not available, measure the vGPU of your card with a DMM. Look at the VID section (Pins 53-60) on the card and write down the first bank (closest to the controller). Use a 1 for a resistor and a 0 for no resistor. Once you have your 8-digit binary number, compare this to the VID table. Find the Voffset that your binary number corresponds to and subtract this from your vGPU. This will give you the reference voltage for the controller. Once you know how much voltage you want, subtract the Vref from your goal. This will give you the Voffset. Look to the tables to determine what binary you need and make the modification to the card (move the resistors)!

 

 

 

 

To simplify the experimental process of trying different VID configurations, it may be wise to device a switching configuration. I would recommend using 8 single pole dual throw (SPDT) switches (example). This allows one input and switches between two outputs. One output would connect to a +5V source and the other output would connect to GND.

 

You would have the circuit below. It allows you to use one resistor and use a SPDT switch to connect it to either +5V or GND. When connected to the +5V source, this corresponds to a logical 1. When connected to GND, it corresponds to a logical 0.

 

5ce650ff_VIDMod_1.png

 

I believe the resistors are 10kΩ, but measure to be sure.

 

 

uPI VID Offset Chart

15c6442d_uPI_VID.png

Edited by xxbassplayerxx
Posted
Fresh released nvidia driver 320.18 does fix the clock issue with Fermi cards. Enjoy Fermi users and Thanks nVidia :)

 

Awesome:) Thanks for the support at Nvidia for this;)

Posted

Cus Forceware "Ney" Edition fa sure!!! Hey please bro try to make them fix that fast! :( Need them before tomorrow -.-

 

Idk if we Dled on .fr or .us but I'm about to try on both...raaaahhh! Why things can't be simple...

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