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  • FireKillerGR
    FireKillerGR

    The thread bump power is strong with this one. Users trolled by web's padawan: 1

  • TerraRaptor
    TerraRaptor

    Okay, here is the story on vpll mod for REX: 1. vpll is controlled with AS324 above PCI-E x1 slot. AS324's non-inverting input is controlled by DAC and we need to disconnect this DAC from pin 5 of AS

  • TerraRaptor
    TerraRaptor

    High vpll moves up the fsbwall on 65nm cpus, low vpll is said to move coldbug down with 45nm cpus. Important note is 45nm cpus will die extremely fast if moving over 1.7-1.8v.

Wow! Thanks for the input so far! Those of you that froze the NB, what did you do for VRM's and SB cooling? When I froze mine, I just set the pot on the flat copper spot on the heatsink since I didn't have anything to put on the rest of the board.

 

DopeLex, is this the link you're talking about?

 

Fun to see so many people sharing s775 goodness. Here's how I insulated the board, I had too much free time back then :D F1EE and some kind of duniek or ryba nb pot.

 

PB050098_zpsfbqrlh1j.jpg

  • Author

Hey everyone, I got the chance to bench this board again last night and had some decent results. I spent most of my time working on frequency for 1M. I was able to pass at 6400 three times but every time, it crashed while opening CPU-Z. Efficiency is way off and it's definitely something I need to work out. To hit max clocks, I have to use PL=15 and memory on Auto. As soon as I try to set those manually, the board stops booting. I didn't spend much time on CPU-Z but I think with a little time and effort, this chip could validate 6.6GHz or so.

 

[hwbot=3110787]submission[/hwbot]

 

[hwbot=3110785]submission[/hwbot]

 

[hwbot=3110788]submission[/hwbot]

 

@crustytheclown, you mentioned a reverse PLL mod to allow me to lower voltages beyond the 1.51V that is currently the lowest setting in BIOS. Is this documented anywhere? I'd love to lower the CB as it is currently -158°C, with CBB at -145°C. Getting closer to C2D full pot benching :cheers:

 

As an update, this is what my settings were:

 

610 x 10 - raise to 635/640 in Windows

266 Strap

PCI-E - 110

Memory all auto

Twister - Lighter

PL - 15

vPLL - 1.51V

VTT/FSB Term - 1.600

vNB - 1.80V

vCore - 1.90V

Spread Spectrums: disabled

 

EDIT: Picture!

 

image_id_1575395.jpeg

Edited by xxbassplayerxx

To get 650fsb boot to windows with rampage (cpu @ss, mobo @stock) I use CPU clock skew delay 400 and NB clock skew delay 100. To get ram working with anything higher than 1:1 I need also to adjust dram skews and nb DDRVref (very critical for my hypers and not that important for bbse).

  • Author

Great info. I was using 300/100 for skews but I was only booting at 610 last night since I was using the 10x multiplier. What kind of settings are you using for nb DDRVref?

the range of -15/-25mv works best (sweet spot is -22.5) with 534 1:2 PL7 strap 333 right now but the sweetpot changes with strap/PL/CL/divider.

ee0114462317701.jpg

 

 

Remove the cap out of those in red circle that is for pll.(i think the second from the right)

You can check with a dmm which one is by measuring them.

Then you have to plug there a e-power,g-power or any short of external voltage regulator to control the pll.

Remember because it is just for pll you do not need to do any hard wiring and grounding to the e-power.just a cable from e-power is enough as cpu pll is not consuming many amps.(ground from the 6pins of the e-power are more than enough).

We used to do it with a home made single phase voltage regulator.

Oh the memories.

  • Author

Crusty, any chance at just doing a reverse trim pot mod? Is there a VSense pin or anything like that? A bit busy today but I may try to look into it.

What a lovely thread! :)

No trim pot is not possible.There is no separate ic for pll control.

There should be at least op amp to give managable pll output. Your idea of connecting epower without desoldering the output of stock power section sounds dangerous and should not work (in best case scenario the stock power section will drop voltage to the level set on epower but that will give stress to stock pll power section).

I think one must cut the trace in any way first.

you have to remove the cap for the pll near the cpu socket and then connect the e-power to it's place.It's very easy and we used to do it way before e-power's were invented.

Okay, I was investigating the means to do pll mod @P5W64 WS a few months ago - there is no dedicated pll circuit there and cpu pll is powered via RC/RLC-filter from vtt or vcc (the same applies to all s370/s478 motherboards as well).

In case of REX there is a dedicated power supply for pll but it should anyway be filtered according to intel specifications. Removing the cap will NOT disconnect that dedicated power supply (caps are parallel to pll circuit) but will worsen the filtering.

 

There must be a kind of trim mod to pll circuit.

 

I wouldn't cut off stock pll power supply and solder epower - even old pentiums were extremely sensitive to this mod and were dying fast even with no over/undervoltage probably because of noise. Instead I would find the pll mod. I may take a look into this @weekend.

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