I.nfraR.ed

@Tzk tRC is 4bit, so from 0 to 15, tRFC is 5bit - 0 to 31. 0 = Auto for both. Currently you have tRC settings up to 31. Edit: Ofcourse I had an error! Had CMOS_ADDR_PORT and CMOS_DATA_PORT switched in readCmosReg macro, which was leading to incorrect CMOS data and it was always setting both tRC and tRFC to 9. It also corrupted my windows installation, because that test memory couldn't handle it at DDR-400. I have corrected the code snippet above. But now everything works great! I have all the settings in the bios, just need to write the code for the rest - trfc, drive strength and slew rate. Instead of mov ebx, 0 I now use and ebx, 0x0 to reset it. Not sure which one is better though, the result should be the same, I think. I will probably be ready with the whole thing tomorrow and will post the full code.

The DFI options are ordered strangely in the bios. Here are them sorted. I will just use a long switch, but haven't decided if I want to list them all or limit the options like you did. The good thing is we can zero both registers and set the value directly, since they are in the order we want them -> 61h 60h. Your option #4 is wrong, should be 0x030C. Not that it matters at all. 04: 0D03 -> 030Dh = 780 cycles 0016 Cycles 0x0010 0032 Cycles 0x0020 0064 Cycles 0x0040 0128 Cycles 0x0080 0388 Cycles 0x0184 0516 Cycles 0x0204 0648 Cycles 0x0288 0776 Cycles 0x0308 0780 Cycles 0x030C 0908 Cycles 0x038C 1032 Cycles 0x0408 1168 Cycles 0x0490 1296 Cycles 0x0510 1536 Cycles 0x0600 1552 Cycles 0x0610 1560 Cycles 0x0618 1816 Cycles 0x0718 2048 Cycles 0x0800 2064 Cycles 0x0810 2336 Cycles 0x0920 2560 Cycles 0x0A00 2592 Cycles 0x0A20 3072 Cycles 0x0C00 3120 Cycles 0x0C30 3632 Cycles 0x0E30 3684 Cycles 0x0E64 4128 Cycles 0x1020 4196 Cycles 0x1064 4672 Cycles 0x1240 4708 Cycles 0x1264

I think this is better and cleaner code. Decided to set each one separately, much easier. Also fasm supports C-style hex numbers, so I will use that. This code is untested and might have some errors, but that's the idea I will use. define PCI_ADDR_PORT 0xCF8 define PCI_DATA_PORT 0xCFC define CMOS_ADDR_PORT 0x70 define CMOS_DATA_PORT 0x71 macro configurePort pci { mov eax, pci mov dx, PCI_ADDR_PORT out dx, eax } macro readPciReg pci { configurePort pci mov dx, PCI_DATA_PORT in eax, dx } macro writePciReg pci, data, mask { readPciReg pci and eax, mask or eax, data out dx, eax } macro readCmosReg reg, mask { mov al, reg ; set CMOS index out CMOS_ADDR_PORT, al ; send register offset in al, CMOS_DATA_PORT ; read CMOS data and al, mask ; mask the data and zero unneeded bits } jmp set_trc set_trc: ; read tRC from CMOS readCmosReg 0x75, 0x0F cmp al, 0 je set_trfc ; else mov ebx, 0 mov bl, al writePciReg 0x80000190, ebx, 0xFFFFFFF0 jmp set_trfc set_trfc: ; read tRFC from CMOS readCmosReg 0x76, 0x1F cmp al, 0 je codeend ; replace with next segment ; else mov ebx, 0 mov bh, al writePciReg 0x80000190, ebx, 0xFFFFE0FF jmp codeend codeend:

I was thinking something like this*, but I don't think it is optimal if I want to reuse same macros for all settings. It also might be a nonsense and not work, it's jut my understanding. Most of these read/write blocks can be macros, but I don't know how efficient is this code compared to simple switches. Edit: I can probably use dx instead of al in those cmos read operations, so I know dx is always used as a variable for data. EAX will hold my original data, EBX will be zeroed and the needed bits will be positioned correctly, depending on data I want to set, sometimes using BX, BH and BL directly, sometimes bitshifting some of them or using some helper variable (edc for example) for the bitshift and then use OR to set the bits on EBX if those bits are in the higher 16bit segment. Something like that... *Sample code: ; ; Let's assume we want to set tRFC and tRC. ; tRC is 90h, tRFC is 91h, so I will arrange them at the same order they need to be set, just for convenience ; each CMOS register is 8bit ; #76h ; | 000 | 00000 | ; | | tRFC | ; #75h ; | 0000 | 0000 | ; | | tRC | mov ebx, 0 ; reset ebx ; read tRC mov al, 75h ; set CMOS index, basically var x = 75h out 70h, al ; send register offset, 70/71 is CMOS, 72/73 is higher/extended CMOS, for our needs we can use both, since we're dealing with lower CMOS registers and one is an alias to the other. in al, 71h ; fetch cmos data to al mov bl, al and bl, 0Fh ; mask the data and zero the high 4 bits, which we probably use for other setting ; read tRFC mov al, 76h ; set CMOS index, basically var x = 75h out 70h, al ; send register offset in al, 71h ; fetch data to al mov bh, al and bh, 1Fh ; mask lower 5 bits ; we now have bx holding both of our values, something like 00011111 00001111 ; cmp bx, 0h ; check both 0 je codeend ; or some other segment ; else we know at least one of them is not 0 ; get register data mov eax, 80000190h ; move address for 32bit register offset, note no leading zero necessary. It's only needed infront of hex values with letter, so the compiler knows it is not a symbol mov dx, 0CF8h ; pci register address port out dx, eax ; set port we want to read mov dx, 0CFCh ; pci register data port in eax, dx ; read register values ; register data is now in eax and cmos values in bx ; cmp bl, 0h ; check if tRC is 0 je set_trfc ; trfc is not 0 then ; else zero tRC in eax and eax, 0FFFFFFF0h jmp set_trfc set_trfc: cmp bh, 0h ; check if tRFC is 0 je write_data ; tRFC is 0, then tRC is not ; else zero tRFC bits in 91h and eax, 0FFFFE0FFh jmp write_data write_data: ; write data or eax, ebx out dx, eax ; write new custom register value jmp codeend ;

I will go through the actual code later and tell you if it is 100% correct, since I read ASM slow and takes me time to comprehend, but you should be careful with eax, al, ebx, edx, etc, since you can overwrite. eax is a 32bit register, then the subset ax is 16 bit register (low 16 bits), which also consists of ah and al (high and low). Changing eg al overwrites the lowest 8 bits in eax. The optimal code should probably keep aex, copy needed parts into other registers(ebx, edx, dx, etc.), reset needed values with masks, then OR with modified value and copy back to al, ah, full ax, etc. Depends on the data. I'm still at work, so my "free" time is limited and it had been very busy lately :(. PS: If I do it in C/C++ first it might help me write more efficient ASM. Perhaps use gcc to convert C code to ASM? Edit: If you read offset 90 to 93, your offset 90h is basically al, while 91h is ah. You can then e.g. manipulate them separately using helper dx for example, apply mask, OR the data and copy changed dx to corresponding subset. And finally push the whole eax if not both trc and trfc CMOS registers are 00h. Otheriwse just skip. This way you can just read and write the whole word (PCI register) once for adjacent offsets, in this case 93h, 92h, 91h, 90h.

Some more info about _item.bin. Not sure if the extra status bits are applicable in our case. I would try some of the other possible statuses to see the effect. Info taken from ROM.by site: http://wiki.rom.by/index.php?title=Award_Inside

Yes, that would savee me some time, although I will have to adapt the item in the system.bin (position in the group, label position, etc.) I've already copied the labels in _EN_CODE.BIN from DFI Ultra-D bios, but my plan is to start from scratch - basically get a clean bios and copy/paste just the option labels I need, then fix the offsets. PS: Wish we had the newer layout with separate _ITEM.BIN

Yep, I use the value of the option to directly set it. Some bitshifts and that's it. But for Tref will use a switch. Will post the ISA option rom code once ready with everything. Now have to start from scratch an remake the options with the new items. It would be good if I can connect them with the other subtimings which are controlled by the parent "Memory Timings" option, but it might not be possible if a custom code is used in bios for this. I just don't have a good understanding how it works before trying it out. I've decided to place them in the same menu, rather than using one of the free options for a submenu label, because I have only 5 available.

I want to add the Tref as well, since it is hard to control it within windows in an easy way - no tool can do that at the moment and you have to tinker with wpcredit/rweverything. Auto Precharge can be changed from Memset and NF2 Tweaker, others are also defaulting to the best setting, so Tref in bios is more useful. The ASM code will have to rely on predefined values, since I don't know how to do math operations But still should work. That would be a long "switch". Will abandon the Command Rate option, since I can't make it work, which means I will still need to support 2 bios versions. Making a 2T version is as simple as replacing the BPL module with one from a stock DFI bios, which is 2T by default. I had a quick look at those "view only" options for IDE, but they look different than a regular label. I guess it is because they are connected to the master item and their value is also changed based on the selection and detected value. Which also leads me to the idea to find if it is possible to add other memory settings in the same set which is controlled by Memory Timings [Manual] option item.

Maybe I'm doing something wrong, but couldn't make it work. Even tried DFI BPL which is 2T by default - same outcome, just in the opposite direction. Maybe there is a sequence to set CR, like the one for CAS above. But perhaps it's just too late at that stage. I will compare saved CMOS registers for 1T and 2T BPL with everything else the same (full manual settings), but I guess DFI has an additional logic for CR. As for the IDE items, I mentioned it before, but still haven't tried if we can use them. Perhaps it would be a problem, since they are connected and controlled by the master item. PS: No difference in CMOS saved data between 1T and 2T on the abit, except for the system time clock. Edit: I've checked some of the tref values and they seem to match yours. Perhaps they are not board-dependant, but defined by nvidia with the BPL. We can borrow the labels for tref from ultra-d bios. Would save time.

Unfortunately doesn't seem to be able to set Command Rate. Hardcoded the other 3 registers. With just Command rate, 1T works, because there's no change in the register. Basically setting the bit to 0 again. When set to 2T I get a blinking cursor after POST. Together with the hardcoded registers, both 1T and 2T don't work. Still can use Auto though, since it skips to the end. Getting a system lock if I try to set any of these offsets in windows. The relevant code: macro writePciReg pcireg, data, mask { mov ebx, data ; move data we want to set mov eax, pcireg ; move address for 32bit register offset mov dx, 0CF8h ; pci register address port out dx, eax ; set port we want to read mov dx, 0CFCh ; pci register data port in eax, dx ; read register values and eax, mask ; mask for data to remove pre-set value, usually the inverse of the data we set or eax, ebx ; add custom value to old register data out dx, eax ; write new custom register value } ; macro getCmosData cmosreg { mov eax, 0 ; reset eax mov al, cmosreg ; set CMOS index out 70h, al ; send register offset in al, 71h ; fetch data } ; ;==================================================================== ; SET COMMAND RATE getCmosData 76h; ; get CMOS register data and al, 3h; ; get lowest 2 bits cmp al, 2h ; skip if auto je codeend ; shl eax, 29 ; we need to set bit 5 in offset 87 ; writePciReg 80000184h, eax, 0DFFFFFFFh ; hardcoded for 2T writePciReg 80000198h, 000764200h, 0FF0000FFh writePciReg 800001F8h, 000004600h, 0FFFF00FFh jmp codeend However, I've found a post in XS that mentions 2 of these offsets for controlling CAS PS: Actually I can set F9, but not the others.

Can someone check what these read on Asus: PCI offset 1T 2T DFI ABIT DFI ABIT B0/D0/F1 87 03 03 23 23 99 21 31 32 42 9A 54 65 65 76 F9 44 45 45 46 DFI is controlled by bios option, Abit 1T is stock, while 2T is my old CPC-OFF modded bios.

Still looking.

Got the menus working yesterday. Will have to test if I can make Command Rate work. If not, will replace it with Auto Precharge. Using CMOS register 75 for Drive Strength and Slew Rate (4 bits each) and register 76 for the rest (2 bits each, so 2 more bits are free from this register). I was thinking that we could sacrifice some of the IDE Channel options that I never seem to touch and reuse these settings for alpha timings. The menus are setup to save the exact value I need for the option rom without using long switches and comparisons. I will only check for "auto". Also, I've verified everything starts from index 0 - the label groups, the label position in the group, the options, so e.g. 12th group would be 0Bh and not 0Ch.

So, apparently, we're updating the forum software directly on production, without testing it beforehand? And we don't announce it. There are isp and jQuery not defined javascript errors preventing anyone from posting. Yes, I can post, because I'm a haxx0r, LoL. Edit: Ah, Leeghoofd posted a note in the news section of the site at least, but I still think it was caused by an update.

Btw, I was thinking if it is possible to set Command Rate with the ISA ROM and add that as an option instead of the e.g. Auto Precharge (we have that in windows tools, even without messing with WCPREDIT). That would be more useful, but I'm not sure if it is too late for CR. Would eliminate the need for a separate 1T and 2T bioses. PS: As for the Gigabyte board - all nforce2 boards need mods to unlock the full potential, especially bios. It looks like an OK board, but will have to mod a bios, add missing capacitors, vcore, vdd and vdimm mods. Then it's just a matter of lucky chipset.

Yes, that is my point. Moving the Auto to last, so it goes Disabled, Enabled, Auto - 0, 1, 2. Then set default option to 02 and in asm code read register saved settings. Compare to 02 instead of 00 and if not equal, set the actual value to the pci register. You can then reuse the same macro for setting all options with direct value from CMOS and only care about the correct shift, mask and register you want to modify. Congrats once again for the achievement. I think this should be the best bios for the Asus board. And we have the correct PCR files for those who don't have the bios options. If we could find how to add new items then it would be perfect, but works this way, too. Mission accomplished, I would say. Now what is left is to tune for different CPUs, e.g. high FSB and performance versions, 2T bios as well. PS: I can buy a Gigabyte GA-7N400 for like 15 euro and wonder if I should try it. The bios has a lot of hidden options that can be unlocked, but would also need a vcore mod, since it is just +5%, +10%. Same 5 free slots for additional items in bios.

Thanks, got it, I think. Abit bioses have 5 free options at the same place. Checked one Gigabyte bios and it's the same there - same 5 options at the same menu. To optimise the asm code, you'd need to move "Auto" to the end of the list and use corresponding Disabled/Enabled or Normal/Fast so they match 0 and 1. For the DS and SR it would work with "Auto" as a first option, since we have the usable options starting from 1 to 15.

Ok, so we are counting only heading label, e.g. "Super Bypass" and starting option label, e.g. "Auto". All the rest are managed automatically, thus 5x2 is 10 in total? And you've used the extra 00 bytes just for padding between different heading labels?

Alright. Think I got everything that needs to be done, just don't have a way to test it at work. I've been very busy with tasks at work and too tired to grasp the concept easily. It took me a while Btw, it should be possible to optimize all these comparisons of the set value. It should be better to just read the setting, e.g. drivestrength, mask it and set it to the register, instead of doing a switch with 16 cases. PS: Perhaps it's a good idea to put all relevant information from the thread into a new document, so it doesn't get lost so easily.

Great work! The asm code is the easiest part for me, since we have a "template" and once everything is in bios, I can write then write the ISA option rom code. I think that I've got how to add the new labels and options and then update the items in "_ITEM.BIN" in the main bios. Will try it when I get back home. You only need to add in _EN_CODE.BIN the starting addresses of the label heading and first option item, right? SuperBypass seems to be enabled by default on NF7, Data Scavenged Rate is also set to Fast. DS and SR are the same for all DIMMs, but DFI sets them differently for the different DIMMs. Will still need to try more combinations, but something like 4/7 and 6/7 works better than the default 3/10. PS: Your code compiles fine under linux.

I don't know. I only have 3 Ultra-B, one has a blown regulator and I use it for spare parts, the other one has some cut traces to the SB, which could be repaired and it might work again. The working one has the bridging SMD capacitor, others don't. Haven't had a problem with it up to 3.7V VDIMM with just a FB mod. But it's not that great of a clocker compared to one of the dead boards. I hate the Ultra-B layout and don't use it often. CPU capacitors are too close to the socket and get on the way of my waterblock. The I/O ports are also very close to the socket. The 20-pin connector is on the other side of the socket and I need an extension to plug the PSU in. On top of that the CMOS reloaded and loading safe defaults is very unreliable, at least on my board.

Ok, checked both settings (F8:2)=Data Scavenged Rate 0=Fast 1=Normal (FC:0)=SuperBypass 0=Disabled 1=Enabled b0/d0/f1 Memory Controller 1 Data Scavenged Rate - offset F8, bit 2; 0 is Fast, 1 is Normal SuperBypass - offset FC, bit 0; 0 is Disabled, 1 is Enabled There's one more setting in DFI bios called "Sync Mode Memory Bypass", but the board doesn't boot when set to Disabled. Might be dependant on memory chips or modules installed. Will test more and report back if I find something. Update PCR file attached. Drive Strength and Slew Rate are correct. b0/d0/f4 DIMM1 - DS is 7Ch and 81h, SR is 7Dh DIMM2 - DS is 67h and 73h, SR is 66h DIMM3 - DS is 65h and 71h, SR is 64h Good thing is I can change all of them (DS, SR, SuperBypass, Data Scavenged Rate) in wpcredit on the fly. 10DE01EB.pcr

Superbypass seems to be b0/d0/f1 offset FC lowest bit. FC:0 (0000000x) 0 - disabled, 1 - enabled Will do more tests on the dfi, but drive strenghts and slew rates seem to be right. b0/d0/f4 row 90 seems to be changing constantly (autorefresh of rweverything shows that), so 91h is indeed incorrect.

I don't know if it is possible at all, but one possible way is to somehow add a new module with all the subitems and just use an unused label that points to it and opens a subpage (a.k.a [Press Enter]) - basically a mini bios in the bios. Award bios editor has the option to add a BIOS Setup Menu. But I don't know how to make such a menu. On a side note, if you want to change the build date and version number of the modded bios file, edit the system bios with hexeditor - search for the date displayed in cpuz. You can find it on 2 places, e.g. the full date 11/11/2004 and the short date 11/11/04. The version number is taken from one of the bios message strings displayed in award bios editor (second one). It seems to split the string with "-" as a delimiter, so last chars will be the version. Then use the cbrom method to compile the bios back.