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I.nfraR.ed

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Everything posted by I.nfraR.ed

  1. Hmm, I had hpet enabled (useplatformclock) as it is required for x264, but it didn't cause the bclk to drop, it happened "out of nowhere" for me and was back to normal after the bios almost killed itself. As you mentioned that though, I can see there are other scores with the same drop in bclk.
  2. Excellent score! You got the same bug with bclk showing as ~98.6? My bios almost committed suicide after that happened, wiped all its profiles and settings, had to start from scratch and it worked afterwards. Also, at some point, I could see all cores, but the scores (dropped in half) were like the second CCD is not there at all.
  3. Ah, the optimization with xp background. :) Great score!
  4. Yeah, I can change it in OS as well, although not much with a board without extra external PLL, but asked because of all the "unreliable/skewed" stuff in Benchmate. What is the difference in memclock compared to ambinent if you have tested? IMC seems to scale quite nicely with cold, but I'm unable to post at over 2200 fclk strap and haven't seen any other result with higher fclk - I think that's the limiting factor for (much) better scores. I can almost train 7000 on the chiller, would probably be ok on LN2. And...do you know when the Tachyon will be available in Germany? That's the only board I'm interested in right now. FYI: I've tested 100 -> 100.50 in OS (internal CPU PLL) and benchmate spits the same unreliable/skewed stuff, although QPC is still displayed as Reliable. I think hwinfo does not detect the bclk correctly as it seems to use the Zen3 algorithm, however it seems to be different on Zen4, e.g. if I set 100.25 with my app, cpuz reports 100.50, while something like 100.1250 is not reflected. Either the granularity is different or there's more in it as the bios allows intermediate values. Need to investigate it, but overall bclk detection on Zen is PITA.
  5. In my testing, 1:2 doesn't really bring anything in terms of clocks. LN2 guys can probably tell more, I only have 2 cold sessions so far and they were with M-die.
  6. So it didn't take too long I can't fight back without LN2 as I'm maxed out on the chiller. Great job and global first place. Btw, bclk adjusted in OS?
  7. Yep, it won't scale much with core clocks, but as IMC scales with cold you might be able to run a bit higher mem clocks? So I'm still interested to see what LN2 run would improve My 7950X seems to coldbugged at -110 no matter what. Has anyone seen fclk higher than 2200 on any cooling?
  8. 6800 is only possible on the chiller (most probably colder, too). 2200 FCLK is where it ends for me, the next multi doesn't even post. 6800 is TM5 stable at these settings, but it is hard to POST with a box cooler. Seems to be limited to 6600 on air. 7000 doesn't POST no matter what, maybe on LN2, but haven't tried with this kit. Too bad I could not solve the -110 CB on this CPU. I'd appreaciate if someone has an idea what I'm doing wrong and want to share some insights. I've only tried one Zen4 on LN2, so I don't have anything to compare with. Maybe it's the chip, but with just 20L it is hard to troubleshoot. PS: Asus tool shows 116/110 (CCD0/CCD1) for this CPU on defaults loaded, althought I've seen it show different values. There's around 50MHz difference in OC capabilities between both CCDs. Best core is 118 SP.
  9. 1:1 is always preferred, but there are other dividers that work, just not on every FSB, you have to find a working combination. There's a PCI lock, so no matter the FSB you have AGP and PCI locked and you can control the PCI bus frequency independently from the FSB. Some of the dividers boot (e.g. lower memory compared to FSB), but they work up to 220 and then you need to clock in Windows. This is how the records are achieved, although I think it would be possible to use TCCD for 1:1. https://hwbot.org/hardware/chipset/nforce2_ultra_400/ There's also an "auto validation bot" in the tweaker, which you can let validate the FSB for you at least for the preliminary testing, then maybe try manually for the last extra MHz, however in my testing the auto bot was able to beat me and validate higher . It can only validate higher FSB, but I can add the opposite direction too (downclocking). You would probably need to tweak the registers though and you definitely need mod bios. My tweaker is not necessarily the best tool for the job, it has a better granularity than Clockgen, but there might be things I don't know, since most of the PLL work done for the tweaker is reverse engineering and "trial and error" method, due to lack of documentation. Luckily there is a linux driver for the PLL I was able to port and extend for my needs. PS: This, for example, has the memory higher than the FSB: https://hwbot.org/submission/2557243 You probably need a 2T bios for TCCD to work at this frequency on NF2 (don't quote me on that though). This is the current record on s.A, I still haven't found the time to try and replicate it: https://hwbot.org/submission/2640212_stelaras_memory_frequency_ddr_sd_ram_305.7_mhz Everybody thought 300.7 was the hard limit, but Greek guys found a way to lift that limit. This platform is my all-time favorite, maybe it helps that my first PC I bought with my own money was socket A based
  10. I had it beaten on chiller already, so this gen seems a little bit faster, but not by much. If my efficiency is not too bad, then one would need 7200+ for sub 4 min on AMD, perhaps it's possible with some of the CPUs of the top guys. I'm not sure how big is the difference between validation and Pi as ZenStates was limited to 70x max multi and I hit that pretty easily Got beaten by my own tools, but I will try again next time. 74x seems to be the highest supported multi according to AMD's RyzenMaster. PS: First one on the bot has 74.75, so maybe 74 is not the max - I don't really know.
  11. I have removed the lower limit. The steps will be stupidly small (0.05MHz), but hopefully it works. I'm not sure what is the lowest supported frequency by the integrated PLL in nForce2, but you can try. Lowest multi should be 3x, but not sure on which generation. https://github.com/torvalds/linux/blob/4cee37b3a4e68c42b867c87a6218e11bc571ba66/drivers/cpufreq/powernow-k7.c#L78 NForce2Xtreme-v1.1-beta19-mod.zip
  12. I have tried and fclk and mem freq didn't matter for the cb. Today, with a remount, I was able to go lower in temps, but didn't have LN2 left to actually run anything. The contact footprint on the pot seemed perfect this time.
  13. You need a VID mod to effectively bypass OVP - by setting a higher VID you lift the OVP trip point to higher value.
  14. It's not possible to change memory timings runtime (within Windows) on AMD AM4/AM5 systems. Userspace programs don't have the privilege level and although you can write the value in the register, it does not get applied. It it was possible, I would have added that functionality into ZenTimings.
  15. I can run 6600, but not for y-cruncher, at least not with "tight" timings. Seems to be limited by the locked mem voltage, the cheaper memory (?) and the score probably should be better if I had tREFI. Maybe the controller is to blame at 6600 for y-cruncher, but I could not get it to run reliably. I have nothing to compare with, just one of each - cpu, motherboard and memory kit. The CPU looks like a good one with very small difference between both CCDs - around 50MHz, maybe good for MT benches. Not sure how common is that for this gen, the difference was usually larger for previous gen. Will have to see what it does with LN2.
  16. Didn't have mich time. This combination was giving me best results in 7zip. DRAM voltage is limited and the board has only one bios. Don't think I can tighten timings much more at 6000.
  17. Let me start. I don't have a 5GHz run and the efficiency is probably way off, plus timings might be plain wrong, but anyway... I only had 1 day to play with the system and not sure when will be able to do again, but hopefully soon. I was able to beat the current AMD top score as well: https://hwbot.org/submission/5125310_
  18. That's a catch, indeed. I was clueless why my score doesn't show up.
  19. Great deal, indeed. However, the usual question for most of the 939 CPUs is "if it scales with cold". A good water/air chip doesn't really guarantee a great result on LN2. Higher multi cpus have a better chance though, before hitting the cold FSB limit, but everything depends on the CB. This, for example, is a dud air chip, that could have been easily discarded, although it scaled massively on LN2 due to very good CB (-90 to -100C range, which I think is very rare for Venice): https://valid.x86.fr/8fed9t I don't reject any s.939 CPU anymore based on ambient tests only.
  20. Maybe back off the volts a little? It seems slow even on inefficient board, indeed. Perhaps the result will be better with a little lower clocks? PS: VCore seems too high for what I've seen (feel comfortable with) when benching K10. On my older screens with the 970A-UD3 board, the vcore under load is much different than what cpuz shows idle, something under 1.9V, because that board has an enormous vdroop.
  21. That's true, however the same applies for "ambient" water cooling. Ambient is not a definitive term. Someone's "ambient" might be below zero (with the rig outside), then other people are in the summer already with degrees over 30 (Celsius) during the day, so it will never be "fair" for everyone, despite the good intentions and idea. If the verification is done by a rig pic only, then good luck verifying anything. At least Alby (@leeghoofd) has shown his "ambient" clearly, can't say about others though :p
  22. I'm a little confused as well. Currently, 25-30C degrees daily temps here and my ambient is 24 right now (no AC). If my only cooling on the bench table is a chiller (with controllable temps), then: 1. Am I allowed to participate at all? 2. If yes, then what should be my chiller set at? 3. Am I allowed to go down in temperature as long as cores are still reading positive temps? Thank you! PS: There seems to be a thread about the competition already:
  23. A good Regor does 4400-4500 1.45 - 1.5V ambient :p
  24. By HTT he means the refclock/fsb in conjunction with temperature. Decreasing the temperature to increase core clock (while using a higher multi and/or voltage) will drop max benchable HTT/FSB, but judging by the current score you have a nice headroom left.
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