Jump to content
HWBOT Community Forums

Lets talk about 32m Low Clock Challenges


Splave

Recommended Posts

Think you need to get of yiur asus high horse,I ask the question is it 100.125,only quoting what rule wrote,I've not got the board to tr

 

Simple answer like it can run lower bull is all what was needed

 

My post wasn't directed specifically to attack you or else I would've quoted you, instead of using 'guys'. Both Rule & Splave mentioned 0.0625Mhz being the lowest step on Asus, which was snowballing into you making wrong assumption.

 

Just wanted to put the correct information out there for existing posters & prevent future wrong assumptions from other people.

Link to comment
Share on other sites

It never has been the only brand that doesn't fluctuate. How about any asus result over 100.0 is cheat since they dont have 100.0625 step? Do you wonder why asrock and giga can do 742+ because the bclk is so stable at 102.9** makes you wonder doesnt it?

 

71664268.jpg

 

was just trying to fix it so it can be fun again, not pointing fingers at vendors, then called a cheat which is lol worthy.

 

Guess I will just be like everyone else and stop trying have fun. /thread

 

no ..Asus don't have a "100.0625 step" that's why you never see anyone going over 5003 on Asus , next step is 100.125=way over the limit and since ASRock does have it almost all ASRock subs come 5004.9 or higher cache since it's so difficult to control/cheat/print screen with the fluctuation on both (CPU/Memory), higher bclk (102.xx) is more manageable on both boards that's why all subs with higher bclk are on equal playing field,you see the advantage/willing to take a chance on Mocf by going near max with that stupid 100.062/different step (bios shows 5003 or 5004 -depends from bios) and you hope you can take that winning screene right bro ? ..as you can see it's not SPI you need to change or blame but BIOS

P.S. maybe instead of blame game you should talk to Nick ..like two ASRock reps and get this fixed

Edited by coolhand411
Link to comment
Share on other sites

no ..Asus don't have a "100.0625 step" that's why you never see anyone going over 5003 on Asus , next step is 100.125=way over the limit and since ASRock does have it almost all ASRock subs come 5004.9 or higher cache since it's so difficult to control/cheat/print screen with the fluctuation on both (CPU/Memory), higher bclk (102.xx) is more manageable on both boards that's why all subs with higher bclk are on equal playing field,you see the advantage/willing to take a chance on Mocf by going near max with that stupid 100.062/different step (bios shows 5003 or 5004 -depends from bios) and you hope you can take that winning screene right bro ? ..as you can see it's not SPI you need to change or blame but BIOS

P.S. maybe instead of blame game you should talk to Nick ..like two ASRock reps and get this fixed

 

You are so right, I've never seen an Asus result over 5003.... Or with high cache...

 

snaphsot0001kbu00.jpg

 

snaphsot00177mucn.jpg

 

But just keep seeing what you want to see, you're good like that.

Link to comment
Share on other sites

Come on, drop the accusations... This is of course not any fault in either of the two MB's. You can run at correct speed with both and you can run with incorrect speed with both. The key aspect is that there is no way to verify CPU-speed. But you can't verify 70% of the benchmarks here anyway. So why is this more of a problem here than anywhere else? I consider running at max bclk to be able to take a legit screenshot to be an optimization. Especially if you look at the rules for the low clock competition:

"CPU Frequency in CPUZ must be lower than 5003 MHz"

 

Consider the alternative. If the rules were: "max fluctuating CPU-freq is 5003 or less", how can you verify that? Should the users wait to catch the highest fluctuating bclk?

Link to comment
Share on other sites

Asus, Asrock all boards are fluctuating so much. Even at 102.9x/103 XTU 742/743 bunnyextraction once you have 4020 MHz cpu, once below 4 GHz. This is stable BCLK?

 

Regarding SPI32M and wrapper - idiotic idea, why? Cause all benchmarks with wrappers are mostly broken. And SPI32M is one of the few reliable and fun benchmarks.

 

In fact Allen you started lc results with higher cache over the limit and it was fine when you were 1st in LC challenge :) Just observing. I don't see anything less fun now in LC than it was in the past, especially when Asrock boards cheated on BCLK which is well known fact in past generations. Just adapt to fluctuating BCLK and that's all, find your proper golden settings and go.

 

I don't see the difference of fun in fact when you run 100.00 or 100.20 MHz, for me SPI32M is same fun and same behaviour so I don't get the problem in fact. If Asrock fluctuates worse than Asus, maybe change board to Asus. For XTU 742/743 we have to use specific boards, best boards for that hw combination. With Skylake SPI32M LC it might be the board which fluctuates the most lol. Life. You are playing the best hw possible for the benchmark (if you can).

 

I don't see anything to fix now, cause it's not broken. If Asrock for you is too slow/doesn't fluctuate enough, you can try M8I and do LC.

 

The only thing which might be a good one - creating a rule that both cache and cores have to be below 5003 limit, cause it's MUCH HARDER or nearly impossible to catch both when you are running really high BCLK.

Edited by Xtreme Addict
Link to comment
Share on other sites

Come on, drop the accusations... This is of course not any fault in either of the two MB's. You can run at correct speed with both and you can run with incorrect speed with both. The key aspect is that there is no way to verify CPU-speed. But you can't verify 70% of the benchmarks here anyway. So why is this more of a problem here than anywhere else? I consider running at max bclk to be able to take a legit screenshot to be an optimization. Especially if you look at the rules for the low clock competition:

"CPU Frequency in CPUZ must be lower than 5003 MHz"

 

Consider the alternative. If the rules were: "max fluctuating CPU-freq is 5003 or less", how can you verify that? Should the users wait to catch the highest fluctuating bclk?

 

exactly this ,if we stick to the rules we wouldn't have this problem in the first place ,the moment they allowed higher cache was when you/me start doing it wrong

 

@Splave this screenshots don't prove much ,some a lazy screens :) (first screen shows both CPU/mem over the limit,second is just lazy-if he waited long enough he would prolly be able to get them both under 5003 or drop one step and still within efficiency,this is one of the quirks of Skylake and I don't thing it could be corrected (clamped on fluctuation )

Edited by coolhand411
Link to comment
Share on other sites

My post wasn't directed specifically to attack you or else I would've quoted you, instead of using 'guys'. Both Rule & Splave mentioned 0.0625Mhz being the lowest step on Asus, which was snowballing into you making wrong assumption.

 

Just wanted to put the correct information out there for existing posters & prevent future wrong assumptions from other people.

 

I can't check 'cause ATM i don't have Asus board at home, but i'm pretty sure of what i'm saying, doesn't matter what can u set in bios. If u can check try to boot at 100.06 and read the frequency with hwinfo.

Can i be wrong i'm human after all, but please stop flamming and try to turn this into a vendors war.

Link to comment
Share on other sites

just to clarify "step" ,I end up booting Gene just to make sure ,on ASUS there is more bclk options ,you can bump it in .01 increments in comparison to the the other vendor where you have 100/100.062/100.125 ...100.062 reaches just over the 5003 limit where on Asus last one would be 100.06

Edited by coolhand411
Link to comment
Share on other sites

I can't check 'cause ATM i don't have Asus board at home, but i'm pretty sure of what i'm saying, doesn't matter what can u set in bios. If u can check try to boot at 100.06 and read the frequency with hwinfo.

Can i be wrong i'm human after all, but please stop flamming and try to turn this into a vendors war.

 

So you people are making assumptions without concrete info & then I am flaming for pointing out that those assumptions maybe wrong...? Seems right.. :rolleyes:

 

Also, I am not the one starting a vendor war, just defending the vendor that I use, because

1) No one else was doing it

2) Indirectly it also makes my results (that i worked very hard for), seem invalid.

 

But apparently defending a vendor is equivalent to starting a vendors war even though i never attacked any other vendor. Please, stop making false accusations.

Link to comment
Share on other sites

^^ don't know where this "vendor war " comes from ,just because you have to name particular vendor to make your point doesn't mean you want to start some "war" ...no one is defending or accusing any vendors just stating facts ,bottom line is there is nothing wrong with SPI or XTU but the HW you using....062 bclk increment in comparison to say .01 will make a big difference

Edited by coolhand411
Link to comment
Share on other sites

exactly this ,if we stick to the rules we wouldn't have this problem in the first place ,the moment they allowed higher cache was when you/me start doing it wrong

 

@Splave this screenshots don't prove much ,some a lazy screens :) (first screen shows both CPU/mem over the limit,second is just lazy-if he waited long enough he would prolly be able to get them both under 5003 or drop one step and still within efficiency,this is one of the quirks of Skylake and I don't thing it could be corrected (clamped on fluctuation )

 

just to clarify "step" ,I end up booting Gene just to make sure ,on ASUS there is more bclk options ,you can bump it in .01 increments in comparison to the the other vendor where you have 100/100.062/100.125 ...100.062 reaches just over the 5003 limit where on Asus last one would be 100.06

 

 

This all makes me laugh ^^

Link to comment
Share on other sites

  • 1 month later...
Over the years hwbot worked with bench manufacturers and made it hard to cheat. Is it possible to implement a clock reader in superpi? Just to show the max clock cpu reached during benchmark.

 

Sent from my LG-D722 using Tapatalk

 

Clock readers are extremely difficult to implement. There is a lot of processor-specific code. And it needs to be updated with every new generation of systems.

 

This is the reason why most benchmarks don't have clock readers - and when they do, it's often inaccurate. CPUz is one of the few applications out that can reliably read the clock speed.

 

This doesn't apply to just the CPU frequency. Any sort of hardware monitoring is extremely difficult to do:

  • All frequencies: CPU, cache, base clock.
  • All voltages
  • Most temperature sensors.
  • Hardware timers: HPET, ACPI.

 

I've personally tried to implement readers for these, but every single one of them requires kernel mode drivers. Which require specialized programming experience as well as driver signing and super-admin access to the machine. And then you have to update everything for every new processor or chipset and maintain a database for all of them which you care to support.

 

CPUz can do that. Few others can.

Link to comment
Share on other sites

Join the conversation

You can post now and register later. If you have an account, sign in now to post with your account.

Guest
Reply to this topic...

×   Pasted as rich text.   Paste as plain text instead

  Only 75 emoji are allowed.

×   Your link has been automatically embedded.   Display as a link instead

×   Your previous content has been restored.   Clear editor

×   You cannot paste images directly. Upload or insert images from URL.

×
×
  • Create New...