Rocket Lake 32M Pi Tweaks for Noobs

[superpatodonaldo]

2 hours ago, Sparky's__Adventure said:

VCCIO mem = 1.45, sometimes higher

VCCSA = 1.45 to 1.65

VCCIO = whatever, not important

Need cold cpu?

[Splave]

no but it does make everything easier to pass

[Broken APEX49]

Hello
Which item is the cache voltage adjustment?
It seems impossible if 46 or more is auto

[Hyperhorn]

Cache voltage = core voltage

46 is pretty much the limit for Rocket Lake on ambient and voltage doesn't really make a difference (at least for me).

[Broken APEX49]

The specific way to actually raise the cache is
Do you mean to raise the CPU voltage?

[BoTSkill]

22 hours ago, GTI-R said:

The specific way to actually raise the cache is
Do you mean to raise the CPU voltage?

To use sub-zero. Rocket Lake doesnt scale on ambient.

[shar00750]

On 6/19/2021 at 12:47 AM, GTI-R said:

The specific way to actually raise the cache is
Do you mean to raise the CPU voltage?

Cache voltage and cpu voltage are the same. Some cpu can do 50/48 on ambient and some can do just 50/46.

There's cpu that need to raise voltage to much for more then cache 46 on air/water but like Allen said, with some cold it's very easy.

[Broken APEX49]

Thank you for letting me know.

[Broken APEX49]

VCCIO mem voltage is 1.45V
It's possible that 1.45V is not enough.
 

[CENS]

Ah the right thread for me

[Broken APEX49]

What are the advantages of DRAM 32GB?

[Mahameru]

3 hours ago, GTI-R said:

What are the advantages of DRAM 32GB?

roughly about .500 second less compared to single rank

[Broken APEX49]

I see.
Let's give it a try.

[GtiJason]

On 8/9/2021 at 8:33 PM, GTI-R said:

VCCIO mem voltage is 1.45V
It's possible that 1.45V is not enough.
 

Could be. I've had to use 1.600v IOM to get 32m pass  3866+ in Gear 1 using 1T
But I can usually pass 32gb Dual Rank 3866 1T Gear 1 at 1.350v IOM 1.4000v SA.
Also SA sometimes needed to be up to 1.7v
2 x 8gb Single Rank dimms are really hit or miss on Gear 1, they either work or do not work.
Gear 2 5000+c15 etc seems to be where they shine
I don't recommend these settings but I've used them a few times on ambient and so far no problems
Keep in mind, you will fail a Lot !

 

Edited August 13, 2021 by GtiJason

[Broken APEX49]

I'm currently challenging a 32GB dual rank, but I'm struggling to even boot at 3600mhz!
I can't adjust the third timing.
It's hard.

[GtiJason]

On 8/13/2021 at 5:41 PM, GTI-R said:

I'm currently challenging a 32GB dual rank, but I'm struggling to even boot at 3600mhz!
I can't adjust the third timing.
It's hard.

On ASRock OCF or APEX XIII ? If it's OCF make sure to enable XMP in bios
And if the dual rank kit is 2 x 16gb B-Die every kit and cpu I've tried can POST 3866 with 1.410v SA and 1.360v IO Memory or less
For the Special (not so) Secret Sauce try playing with ODT resistances. Try
ODT WR (A1) 120
ODT WR (B1) 120
ODT NOM (A1) 34
ODT NOM (B1) 34
ODT PARK (A1) 48
ODT PARK (B1) 48

You say you have problems with the third timings well look at this image I posted above and copy it.
Try leaving tWRRD_sg and tWRRD_dg on AUTO to start as they are tied to other timings such as
WTR_L, WTR_S, WR, CWL maybe Frequency, CAS Latency (CL) and Command Rate (CR)
Could even try to leave things like WTR_L and WTR_S on AUTO
and maybe even WR because bios does not show tWRPRE or tCCD and
WR = WRPRE - ( CWL + CCD ) . CCD is usually 4 btw
Example WRPRE 28 - ( CWL 9 + CCD 4 )
28 - 13 = 15 so in this case tWR is 15

Last thing is some memory dividers just won't boot or are way harder. So just try a lower or higher divider with BCLK to get desired frequency 

EDIT: Just want to clarify things a step further
To clear things up a bit .  .  .  
On some boards, tWR in the UEFI does nothing and instead needs to be controlled through tWRPRE (ASUS). Dropping tWRPRE by 1 will drop tWR by 1, following the rule tWR = tWRPRE - tCWL - 4
On Intel, tWTR_S/_L should be left on auto at first and controlled with tWRRD_dg/_sg respectively. Dropping tWRRD_dg by 1 will drop tWTR_S by 1 and Dropping tWRRD_sg by 1 will drop tWTR_L by 1.
Changing tCWL will affect tWRRD_dg/sg and thus tWTR_S/L. If you lower tCWL by 1 you need to lower
tWRRD_dg/sg by 1 to keep the same tWTR values. This (lowering tCWL) might also affect tWR as mentioned above.

Further Simplified using the Food Chain template haha!

       CWL               If you lower this by 1         
WRRD_sg/dg        these lower by 1
   WTR_L/S           and that makes these lower by 1
        WR                which raises this 1 by relation of the rule tWR = tWRPRE - tCWL - 4
 

Edited August 16, 2021 by GtiJason

[Broken APEX49]

I'll be referring to this when I use OCF.

[GtiJason]

42 minutes ago, GTI-R said:

I'll be referring to this when I use OCF.

I updated the post above so if you took notes they should be changed for better understanding

To clear things up a bit .  .  .  
On some boards, tWR in the UEFI does nothing and instead needs to be controlled through tWRPRE (ASUS). Dropping tWRPRE by 1 will drop tWR by 1, following the rule tWR = tWRPRE - tCWL - 4
On Intel, tWTR_S/_L should be left on auto at first and controlled with tWRRD_dg/_sg respectively. Dropping tWRRD_dg by 1 will drop tWTR_S by 1 and Dropping tWRRD_sg by 1 will drop tWTR_L by 1.
Changing tCWL will affect tWRRD_dg/sg and thus tWTR_S/L. If you lower tCWL by 1 you need to lower
tWRRD_dg/sg by 1 to keep the same tWTR values. This (lowering tCWL) might also affect tWR as mentioned above

Edited August 16, 2021 by GtiJason

[Broken APEX49]

9 hours ago, GtiJason said:

ASRockOCFまたはAPEXXIIIでは？OCFの
場合は、BIOSでXMPを有効にしてください。デュアルランクキットが2 x 16gb Bの場合、私が試したすべてのキットとCPUは、1.410vSAおよび1.360vIOメモリ以下のPOST3866を使用
できます。だから）シークレットソースはODT抵抗で遊んでみてください。試してみてください
ODT WR（A1）120
ODT WR（B1）120
ODT NOM（A1）34
ODT NOM（B1）34
ODT PARK（A1）48
ODT PARK（B1）48

あなたがうまくこれを見て第三のタイミングに問題があると言います上に投稿した画像をコピーします。
tWRRD_sgとtWRRD_dgをAUTOの
ままにして、WTR_L、WTR_S、WR、CWLなどの他のタイミング（周波数、CASレイテンシ（CL）、コマンドレート（CR）など）に関連付けられているため、開始してみてください。

BIOSがtWRPREまたはtCCDを表示せず、
WR = WRPRE-（CWL + CCD）であるため、 WTR_LやWTR_SなどをAUTOに、場合によってはWRに残そうとすることもできます。CCDは通常
4btwです。例WRPRE28-（CWL 9 + CCD 4）28-13
= 15したがって、この場合、tWRは15です。

最後に、一部のメモリ分周器が起動しないか、非常に困難です。したがって、BCLKでより低いまたはより高い分周器を試して、目的の周波数を取得してください。 

編集：物事をさらに明確にしたいだけです
。。。  
一部のボードでは、UEFIのtWRは何も行わず、代わりにtWRPRE（ASUS）を介して制御する必要があります。tWRPREを1ドロップすると、ルールtWR = tWRPRE --tCWL-4に従って、tWRが1ドロップします。
Intelでは、tWTR_S / _Lは最初は自動のままにして、それぞれtWRRD_dg / _sgで制御する必要があります。tWRRD_dgを1ドロップすると、tWTR_Sが1ドロップし、tWRRD_sgを1ドロップすると、tWTR_Lが1ドロップします
。tCWLを変更すると、tWRRD_dg / sgに影響し、したがってtWTR_S / Lに影響します。tCWLを1下げる場合は
、同じtWTR値を維持するために、tWRRD_dg / sgを1下げる必要があります。これ（tCWLの低下）は、前述のようにtWRにも影響を与える可能性があります。

食物連鎖テンプレートを使用してさらに簡略化ハハ！

       CWLこれを         
1WRRD_sg / dg下げると、これらは1
   WTR_L / S低く
        なり、ルールtWR = tWRPRE --tCWL-4の関係により、これは1WR高くなります。
 

ODT?

[sabishiihito]

On Die Termination

[Broken APEX49]

Well, the specs look like this now.

[GtiJason]

7 hours ago, GTI-R said:

Well, the specs look like this now.

That's awesome man !
The "best" Dual Rank all ambient Samsung run I have is this. tRCD/RP at 11 seems impossible with this kit.
OS is beyond trashed from testing many kits of memory
Has seen at least 125 NEIR and 25 Not Convergent in Sqr's .  ?

[Broken APEX49]

Difficult to set dual rank.
Unable to complete pi
Need to increase normal IO voltage as well?

[l0ud_sil3nc3]

14 minutes ago, GTI-R said:

Difficult to set dual rank.
Unable to complete pi
Need to increase normal IO voltage as well?

No need to touch regular IO voltage. Dual rank needs a healthy dose of SA and IO M depending on your cpu and what bench you're running.

 

[Broken APEX49]

The OS is booting. But the pi stops after about 3 loops. io mem is 1.65v I've increased SA to about 1.68v.