ROG Crosshair VI

[Ace123]

Looks alot like mine

[ReDXfiRe]

Having issues with both 0082 and 0083 BIOS with CMU16GX4M2C3200C16R RAM Kit. Not going past 2133mhz. With 1002 it was running at 4.042ghz stable and RAM running at 3200mhz. It's not recognizing the manual input of RAM timings.

[HattoWW]

Looks alot like mine

Hi there, very nice scores tbh. Couldy you share your Bios settings with screenshots?

 

Mine best is CPU@4100 Mhz with ram@3600mhz but its not stable.

 

Thank you

[flanker]

Did tested someone this? In 32M example? TWO (2+0) could be ideal choice

[chew*]

Did tested someone this? In 32M example? TWO (2+0) could be ideal choice

 

try using ref clock with 2+0 then tell me if you still think its an ideal choice

[zeneffect]

Did tested someone this? In 32M example? TWO (2+0) could be ideal choice

 

Yea don't do that on biostar gt7..

Then leave ln2 switch on and wonder why flashing bios takes over an hour lol

[flanker]

for fun, almost 60k points in R10 at stable settings (memory are bad, 2933 MHz no post in several times and BIOS 1001)

 

[delly]

@elmor

any news about OC Panel I firmware?

[dsquitieri1]

Has anyone tested what gives better fps in games, higher bclk with higher ram speed or lower ram speed with higher oc with 100 bclk ? Just curious, i can get 4.05 with bclk at 105 and ram at 3360 14 14 14 36 timings , can also get 4.05 with bclk at 100 but can dip timings to 11 11 11 11 28 and ram at 2933 , feels like the latter is faster but not entirely sure

 

Sent from my SM-N920V using Tapatalk

[dsquitieri1]

Cool!

 

Sent from my SM-N920V using Tapatalk

[elmor]

@elmor

any news about OC Panel I firmware?

 

OC Panel II firmware works on OC Panel I

[Reltdeats]

Probably setup related that is the same SSD I used in the build I posted earlier and it runs into windows with no issues with BCLK all the way up to 148mhz.

 

I'm 100% sure that is a driver related issue now. Disabling Fast Boot from windows 10 (not from bios) will prevent any DRIVER_POWER_STATE_FAILURE with default bios settings.

 

Its a PCIe controller driver issue, I have seen the same error using an internal Wifi card without M2 drive.

 

So its a problem with AMD chispet drivers, if someone have contact with them, please notify this error. They have not updated chisped drivers since 3/10/2017.

[flanker]

guys, best BIOS for 32M? Its possible to do 32M in "Performance bias"?

[zeneffect]

guys, best BIOS for 32M? Its possible to do 32M in "Performance bias"?

 

1001imo. Bias is auto.

Edited April 18, 2017 by zeneffect

[flanker]

So, why is with new Agesa Superpi a bit slower?

[zeneffect]

So, why is with new Agesa Superpi a bit slower?

 

Chew* had mentioned this on xs. Something slacked in timings that is not visible. As compatibility increases for higher clock potrntial, efficiency decreases. It should be fixable once and opens up sub timings, but for now 2400 strap on 1001 is what is working best for me ATM.

[flanker]

I hope, AMD will really unlock second and third timings for BIOS workers. I keep 1001 some time and we will see.

[Amd_ocer]

hi guys,

 

So I read and went through the C6H XOC Guide v05 entire guide and I have some questions.

 

The stock BCLK is of course 100 (which applies to mem, CPU , etc)

 

My question is: what is the advantage (if any) to increase that BCLK to 114, or 116, or 120 when it comes to memory overclocking..? I mean we have 100 BCLK that can work with DDR4 2400 all the way to DDR4 3600, so can someone please explain to me why would we want to increase the BCLK?

[Johan45]

At present highest memory divider is 3200 on only some(CHVI) boards. On top of that the subtimings are locked out . The only way to tighten sub-timings at present is to use a lower divider like 2666 and use BCLK to raise ram speed after that. That's the only way to get a mem clock like this

 

[Amd_ocer]

^^ In your example, what is the "stock" DDR specs and speeds?

 

Would not raising BCLK to 140 causes everything else to be affected, like PCI devices, and so on... Seems like counter-productive at that point.

[Johan45]

Stock DDR is G.Skill 3600 Cl17-18-18 from December 2015.

The PCIe bus drops to Gen2 automatically and will drop to Gen 1 but I'm not at that threshold. It will affect transfer speeds but not that badly besides you're not likely doing 3D benchmarks on this platform any way

[Amd_ocer]

What I dont understand is the calculation of the mem divider vs the memory frequency on Ryzen. For example, if I have a kit that is 3200CL14 or CL15 and my target DRAM is also 3200CL14, and the board supports a divider of 3200, why would I mess with the BCLK at that point?

 

In which case one would lower the divider to 2666 from 3200 on a 3200CL14 or 3200CL15 kit, and for what purposes?

[Amd_ocer]

Here is another example: why would someone with the following kit F4-3200C14D-32GTZSW use a BCLK of 131.4 and a divider of 2133, just to reach a DDR4 frequency of 2803, when his kit supports the 3200 divider in the first place..

 

Lastly, I read that when increasing the BCLK on the CH6 board it would automatically downgrade the PCIe to GEN 2, is that true, or it would have to be manually changed?

[I.nfraR.ed]

Currently, we don't have control over any memory timings, except the main 5.

AMD's AGESA code provides "tables" with different sets of timings depending on the divider used.

Whenever you use e.g. 2666 divider, you always get the same set of timings and you can only change main 5 in bios - all other subtimings are what AMD thought suitable.

Higher divider - slacker timings - higher latency. If you want the best possible results, you have to increase bclk and use lower divider (with tighter subtimings).

 

There's another thing. I have tried 4x8 single rank Samsung B-die and it is impossible to boot at anything lower than CAS18 on 3200 divider, so if I want to run 3200C14 with four sticks and decent timings, I have to use lower divider in combination with bclk. There's something wrong with higher dividers. Same thing applies to 2x16 dual rank, I think, but have no such sticks to verify. 3200 with CAS lower than 18 basically only works with 1 sngle rank dimm per channel (2x8/2x4).

 

Many people with high density kits have problems booting with higher dividers at all, so this is another reason to use lower dividers.

 

PCI-E drops to GEN2, but I don't think this is a big issue even for 24/7. For benching you can go much higher in bclk, but for 24/7 it is not really recommended.

Edited April 21, 2017 by I.nfraR.ed

[Amd_ocer]

Currently, we don't have control over any memory timings, except the main 5.

AMD's AGESA code provides "tables" with different sets of timings depending on the divider used.

Whenever you use e.g. 2666 divider, you always get the same set of timings and you can only change main 5 in bios - all other subtimings are what AMD thought suitable.

Higher divider - slacker timings - higher latency. If you want the best possible results, you have to increase bclk and use lower divider (with tighter subtimings).

 

There's another thing. I have tried 4x8 single rank Samsung B-die and it is impossible to boot at anything lower than CAS18 on 3200 divider, so if I want to run 3200C14 with four sticks and decent timings, I have to use lower divider in combination with bclk. There's something wrong with higher dividers. Same thing applies to 2x16 dual rank, I think, but have no such sticks to verify. 3200 with CAS lower than 18 basically only works with 1 sngle rank dimm per channel (2x8/2x4).

 

Many people with high density kits have problems booting with higher dividers at all, so this is another reason to use lower dividers.

 

PCI-E drops to GEN2, but I don't think this is a big issue even for 24/7. For benching you can go much higher in bclk, but for 24/7 it is not really recommended.

 

Got it. So it is mainly because the current 3200 divider is not working as expected, otherwise we would not theoretically need to go 2666 in order to have better mem frequency or latency. So maybe in the future that would be fixed by BIOS updates and we would not have to go to a lower mem divider, OR raise the BCLK. Now it all makes sense.

 

Lastly, are the memory latency issues with having 2 CCXs been addressed yet? I use a lot of VMs and I would like to know how Ryzen fairs in terms of fast memory transfer between its own CCXs and the main memory...