The Official Team CUP 2018 DDR stage thread:

[Leeghoofd]

I need to see the memory being used either in the screenshot or in the CPU-Z link, other bios maybe ?

[Mr.Scott]

That's an old version of CPUz.

Try the new one first.

[alexmaj467]

21 hours ago, StingerYar said:

Stage 8 - Memory Frequency Dual channel

What about blank SPD pages, even with other versions of CPU-Z? The presence of SPD tab is mandatory (even if info is not readable), or you have to find different software that can read them correctly?

responded on your command forum.

You need to run the old version 1.78 without closing it to run the new version 1.83 or 1.86 and the new version will tab SPD with information..

[Mr.Scott]

I didn't do anything special. Loaded 1.85 and had SPD .

[Bones]

Quick question - In SC1: DDR1 stage 8 of the DDR comp, are subs ran with a Socket 754 system allowed?

[Leeghoofd]

as long as it is dual channel all platforms are allowed sir

[cbjaust]

2 hours ago, Bones said:

Quick question - In SC1: DDR1 stage 8 of the DDR comp, are subs ran with a Socket 754 system allowed?

 

54 minutes ago, Leeghoofd said:

as long as it is dual channel all platforms are allowed sir

Well that rules out socket 754 then.

[Bones]

Thanks for the reply ? - I've already beaten what I'll ever do with a 754 so it wasn't really about me so much.

More like in the case of someone that would only have a 754 system and nothing else to run DDR with and thought to get clarification about it before it became an issue.

[Splave]

Can someone inform me more about 250 divider? I have 4 chips and none will enter os. Tccd on sli-dr tried countless bios. 1:1 works up to 350ish. Ive seen others using 148/165 and it working although no fx singles cores. 

[Noxinite]

It only works with Venice and Manchester cores I think.

[cbjaust]

SanDiego and Denmark too.

Edited September 5, 2018 by cbjaust

[Mr.Scott]

Has more to do with the multiplier used than the core.

[Splave]

core mulitplier? wtf haha thanks for the hints men i'll get back to work I Guess

 

it trains and all, just sits at that screen that usually says DMI ok before OS splash screen 

 

@Mr.Scott what time should I come over for my lesson, or are you coming here haha

Edited September 7, 2018 by Splave

[DR4G00N]

35 minutes ago, Splave said:

core mulitplier? wtf haha thanks for the hints men i'll get back to work I Guess

 

it trains and all, just sits at that screen that usually says DMI ok before OS splash screen 

 

@Mr.Scott what time should I come over for my lesson, or are you coming here haha

Your running them in the orange slots right? May just be the board not perfectly liking your specific set of TCCD even.

My SLI-DR Expert for example absolutely hates my Centon Winbond UTT but works great with my Kingston CH-5.

Edited September 7, 2018 by DR4G00N

[Splave]

1 minute ago, DR4G00N said:

Your running them in the orange slots right? May just be the board not perfectly liking your specific set of TCCD even.

My SLI-DR Expert for example absolutely hates my Centon Winbond UTT but works great with my Kingston CH-5.

Yes orange slots, I think you might be right. Had teammate send a cpu that he was able to do it on to rule out issue with my board or mems. Would be odd though since none of the 5 chips I tried worked. Seems maybe it is the mems

[yosarianilives]

54 minutes ago, Splave said:

core mulitplier? wtf haha thanks for the hints men i'll get back to work I Guess

Memory is set by a divider based on core multiplier on k8 chips. Certain dividers require even cpu multiplier and certain dividers require odd cpu multi. Also if you have option for half multiplier don't use it. All my testing found that it completely destroys scores, likely due to whatever screwy mem divider it has to run. Not sure if this is what Mr. Scott is referring to as I've only done AM2, but I know that 939 is similar as far as how the memory divider works.

[Mr.Scott]

2 hours ago, yosarianilives said:

Memory is set by a divider based on core multiplier on k8 chips. Certain dividers require even cpu multiplier and certain dividers require odd cpu multi. Also if you have option for half multiplier don't use it. All my testing found that it completely destroys scores, likely due to whatever screwy mem divider it has to run. Not sure if this is what Mr. Scott is referring to as I've only done AM2, but I know that 939 is similar as far as how the memory divider works.

You very smart guy.

[Splave]

Welp must be my mem. Used a buddies chip just sits here then cycles again. Off to find more ddr I guess 

[Alpi]

It can be more things even set a half multi on ht can solve it but usually it means Your ram can't work on actual settings.

[Mr.Scott]

21 minutes ago, Splave said:

Welp must be my mem. Used a buddies chip just sits here then cycles again. Off to find more ddr I guess [/quote]

 

What sticks were those?

And what bios are you on?

Edited September 8, 2018 by Mr.Scott

[Alpi]

If You hang on rams or struggling with them time to time You should try another bioses. It's one of the most important step to find a good bios for Your config. Ofc You can change many things but some main behaviours depends on bios. Huge changes can be happened from a bios change. 

Edited September 8, 2018 by Alpi

[Splave]

Thanks for the help guys. 

These are mushkin blackline tccd I popped the top off. 

Bios is NF4LD329 seemed to be best at the 1:1 that I tried. Tried the newer modded and unmodded ones

Anyays fixed my boot issue. 

Acpi SRAT disabled boots like cake. 

C'est la vie, mon chérie atleast I'm having fun right? 

[Mr.Scott]

U have message.

[Alpi]

16 hours ago, Splave said:

"C'est la vie, mon chérie atleast I'm having fun right? "

939 is always enjoyable for me. Endless platform (if You own a Dfi board.. ) with many variables. It's good to see You enjoying this ! (Also some other names too) Anyway, we can see some insane submissions ! Insane clocks submission after submission !! 

 

[Mr.Scott]

Cannot sub in GPUPI 100M.

Error says I need to use ver. 3.3. Is that true? I thought we were only allowed 3.1 and 3.2.