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TerraRaptor

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Everything posted by TerraRaptor

  1. Okay, here is the story on vpll mod for REX: 1. vpll is controlled with AS324 above PCI-E x1 slot. AS324's non-inverting input is controlled by DAC and we need to disconnect this DAC from pin 5 of AS324 and set the voltage on this pin manually. I had issues trying to lift the leg of AS324 and broke it so I had to completely remove AS324 and replace it with LM324 (same as AS324): 2. Before soldering LM324 back I have lifted up the 5th pin of this IC (the picture also indicates how to connect multiturn trimpot to lifted pin of LM324/AS324): 3. 1st and 3rd pins of trimpot should be connected to 3.3v and ground respectfully, middle pin should be connected to lifted pin of LM324: 4. The result is you can set any voltage you want in 0-3.2 range for pll, turning the trimpot: Tips: 1. You can use any trimpot however I recommend using >1kOhm. It acts as resistor divider that allows setting voltage on the middle pin in the range from ground to 3.3v (or 12v if you connect your trimpot to 12v). 2. I recommend that you use 65nm cpu - in case something goes wrong (wrong point of trimpot connect or disconnected wire etc) the maximum of 3.3v will go to cpu pll which is still safe for some time for 65nm cpus. Or, to be maximum safe, use no processor at all and check the pll voltage with motherboard started on the back side of motherboard here: 3. To be on a safe side and get 1.65-1.7v on initial startup I recommend that you set trimpot in the middle (so for 1kOhm resistance between left pin of trimpot and middle pin should be 0.5kOhm, for 10kOhm trimpot - 5kOhm etc).
  2. I have issues with my REX not posting after testing SS on nb (probably mositure somewhere under socket/nb) so cannot be 100% sure. Should complete the vpll mod later today if I fix an issue. vpll transistor is on the back side of the motherboard and I was not able to track the IC that controls the gate of this transistor. I think there may be two options - to control the gate with external resistor divider (this mod will allow switching back to normal mode) or trying to tie the gate to ground with resistor (but this will depend on PWM IC if it will stand it).
  3. It is. s478 cpu with adaptor for lga775 board
  4. for reference clock stage would it be fine if I use s775 mobo with adaptor?
  5. I can confirm cold on nb helps and wolfdales are bclk-dependant on temperature. With cpu@186W tec and nb @ss I can now boot to windows with 650fsb and high memory multies - however tec is not enough to make me run any tests (anyway, it was not able to boot windows with water cooling only @650fsb). Actually, cpu requires 1.75 vtt and gtl tweaking to go that high with water/tec. Maybe that is cpu that sucks but this wolfdale really scales with cold in terms of fsb in my test.
  6. Not really. I was looking for a bios that allows good overclockability of cedarmills and flashed 0206 as it is known to be amongst the best one for it (however didn't check if it helps with 65nm netburst). Performance is in line with 1301 if you set everything manually (and yet I need to work on baredit).
  7. I think perftune to low priority will help you George. Can you track if PL indeed amends the priority of p95-bench.exe - it should state it in the log. I don't bench modern platforms anymore but I think it is either you doing something wrong or the OS build which is not that much affected with this bug.
  8. Okay, better waza and 10.49.672 now)
  9. I demonstrated this "tweak" at AOOC qualifier to der8auer a year ago. Thought this was fixed(( http://forum.hwbot.org/showpost.php?p=328647&postcount=73
  10. I also have performance issue in xtu with g550jk and this processor(
  11. Anyone knows if E8xxx are fsb limited with air? I have put my single stage on NB (-28C load) and cannot jump over 630fsb (630*6) with cpu cooled by all-in-1 water cooling at any strap/setting (before, I was able to push it to 660fsb with 1:1 cooled by ss). CPU itself is capable at least 4400-4600 at this cooling. Also, it seems like I should use single sided memory to go high memory clocks over 600 mhz fsb.
  12. I guess GPUZ won't detect nvstrap so that can be easily faked into GF2.
  13. I would create a reputation system for reporting. User with good repatation may report, user with bad rep may not. Reputation votes for user are available to mods only. So after reporting 10 good subs user is banned from report functionality.
  14. I hope it is warm up only?) Great scores!
  15. По руÑÑки - к Ñтарым результатам неприменимы Ñовременные правила (вплоть до 2009 Ð´Ð»Ñ Ð²Ñех теÑтов, Ð´Ð»Ñ Ð°ÐºÐ²Ð°Ð¼Ð°Ñ€ÐºÐ° до 2012). Правила менÑлиÑÑŒ, Ð´Ð»Ñ Ñ‚ÐµÑ… времен результаты были оформлены доÑтаточно правильно, чтобы получать меÑто и очки. Ðовые правила не имеют обратной Ñилы, поÑтому нефиг жаловатьÑÑ Ð½Ð° результаты, датированные более ранним временем, чем Ñ‚Ð²Ð¾Ñ Ñ€ÐµÐ³Ð¸ÑÑ‚Ñ€Ð°Ñ†Ð¸Ñ Ð½Ð° боте. Ферштейн?
  16. Anyone here tried TEC cooling for NB? I want to check my REX with 186W TEC cooled by cold water (+10-12C) to see if it will allow me to go higher than 650-660mhz posssible with stock heatsink. I also have issues running high fsb over 600-620mhz with non "1:1" memory dividers and hope cooling will resolve this. I know the best is to put pot on nb but I need first to setup memory properly (i.e. 666fsb strap 400 2:3) before going ln2.
  17. Okay, I was investigating the means to do pll mod @P5W64 WS a few months ago - there is no dedicated pll circuit there and cpu pll is powered via RC/RLC-filter from vtt or vcc (the same applies to all s370/s478 motherboards as well). In case of REX there is a dedicated power supply for pll but it should anyway be filtered according to intel specifications. Removing the cap will NOT disconnect that dedicated power supply (caps are parallel to pll circuit) but will worsen the filtering. There must be a kind of trim mod to pll circuit. I wouldn't cut off stock pll power supply and solder epower - even old pentiums were extremely sensitive to this mod and were dying fast even with no over/undervoltage probably because of noise. Instead I would find the pll mod. I may take a look into this @weekend.
  18. There should be at least op amp to give managable pll output. Your idea of connecting epower without desoldering the output of stock power section sounds dangerous and should not work (in best case scenario the stock power section will drop voltage to the level set on epower but that will give stress to stock pll power section). I think one must cut the trace in any way first.
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