Massman Posted April 11, 2013 Posted April 11, 2013 You can download the .pdf slides as shown at IDF here: https://intel.activeevents.com/bj13/scheduler/catalog.do (just search for "overclocking"). There's a bunch of other interesting material there as well. All the information in this article should be public knowledge, no NDAs broken. Quote
NoMS Posted April 11, 2013 Posted April 11, 2013 If BCLK OC means that the times of fun overclockable cheap chips (Haswell based Celeron's/Pentium's) like the ones of "775 era" is back, the only thing I have to say about this platform is: Quote
Crew Leeghoofd Posted April 11, 2013 Crew Posted April 11, 2013 Why do we get tips to bench Ivy ? so confused by this... Quote
Splave Posted April 11, 2013 Posted April 11, 2013 If BCLK OC means that the times of fun overclockable cheap chips (Haswell based Celeron's/Pentium's) like the ones of "775 era" is back, the only thing I have to say about this platform is: there are probably steps like x79 100, 125, etc for the bclk and they might not be as flexible straying away from those steps. I assume they would lock that down on cheap chips..just conjecture though Quote
NoMS Posted April 11, 2013 Posted April 11, 2013 (edited) there are probably steps like x79 100, 125, etc for the bclk and they might not be as flexible straying away from those steps. I assume they would lock that down on cheap chips..just conjecture though Sure, but it's always better than actual 100+/-10% BCLK OC that we have with 1155 Sandy/Ivy and that would make the cheap chips oc able. But being somewhat realistic, I don't expect to see Intel allowing BCLK OC on these cheap chips too... But well... The hope is the last thing to die! Edited April 11, 2013 by NoMS Quote
der8auer Posted April 11, 2013 Posted April 11, 2013 I guess only the K-suffix CPUs will have the option to change the bclk. Quote
TaPaKaH Posted April 11, 2013 Posted April 11, 2013 overclockable or not, low-end CPUs are only good for hardware points Quote
Massman Posted April 12, 2013 Author Posted April 12, 2013 Overclocking has become just another product feature that Intel can charge for. Just like - hyperthreading - amount of cores - amount of cache - type of IGP - virtualisation - dram ratios And so on. There has been no confirmed (or leaked) product information regarding the correct configuration of the SKUs, just guesses, so we can only make assumptions here. But it seems fairly obvious that the non K-sku processors will not have the option to play with PEG:DMI (bclk gear ratio) settings. Quote
Bobnova Posted April 12, 2013 Posted April 12, 2013 The 3820 has gear ratios despite being a non-K, so some of 'em might. Almost certainly not the low end stuff though. Quote
Massman Posted April 12, 2013 Author Posted April 12, 2013 The 3820 has gear ratios despite being a non-K, so some of 'em might. Almost certainly not the low end stuff though. Hah, same response I had . I was made aware of the fact that the Core i7 3820 was part of the most high-end desktop platform and that Haswell is a replacement for the mainstream platform. Between the lines, it probably meant that all non-K sku CPUs built for a high-end X-chipset will have additional overclocking options compared those for a mainstream Z-chipset. Quote
Administrators websmile Posted April 12, 2013 Administrators Posted April 12, 2013 Interesting info, thanks for sharing, PJ - maybe decision to skip Haswell was made bit too soon Quote
xoqolatl Posted April 12, 2013 Posted April 12, 2013 IDF 2012 docs say that L3 cache is on ring frequency and power domain. IDF2013 China docs say L3 is on core domain. I think the former is correct? BTW, what you call eDRAM is not on-die (it's a separate die on the same package), also the small e for embedded is not exactly correct, since it's a separate die Quote
flanker Posted April 12, 2013 Posted April 12, 2013 but.. I thought eDRAM will be only mobile CPUs (GT3), or not? Quote
Massman Posted April 13, 2013 Author Posted April 13, 2013 IDF 2012 docs say that L3 cache is on ring frequency and power domain. IDF2013 China docs say L3 is on core domain. I think the former is correct? BTW, what you call eDRAM is not on-die (it's a separate die on the same package), also the small e for embedded is not exactly correct, since it's a separate die Thanks for the corrections. L3 must be on Ring frequency as it's shared between all cores. There wasn't that much information on the eDRAM - even behind-the-scenes. All the info we got was "additional cache", "in-house design" and "super dooper fast". Quote
Bobnova Posted April 13, 2013 Posted April 13, 2013 SB/IB the L3 runs at core speed, doesn't it? It could be anywhere! Quote
chispy Posted April 14, 2013 Posted April 14, 2013 Very nice article , thanks for sharing Pieter. Quote
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